US4716319A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Switched capacitor filter for low voltage applications
Assignee: Motorola Solutions Inc
•
Filing: 1986-08-04
•
Granted: 1987-12-29
•
Expires: 2006-08-04
Abstract
Abstract An improved switched capacitor circuit configuration is disclosed which exhibits improved low voltage supply operation and improved charge injection cancellation performance. In the preferred embodiment of a switched capacitor integrator, the improvement is realized by the particular configuration of a switched tub switch on the input, single N-channel devices at the summing junction, skewing the analog ground V AG downward, and delaying the clock signals to turn off the switches at the summing junction before the charge injection of the switched tub switch is realized.
Inventors
- 👤 Michael E. Rebeschini
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:45
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/18; G06G7/184; G06G7/186; G06G7/1865; H; H03; H03F; H03F1/00; H03F1/30; H03F1/303
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
227 words
A switched capacitor circuit having an input node, an output node, and a reference node, said circuit comprising in combination: a capacitor having first and second plates; a gain device having an input port and an output port, said output port coupled to said circuit output node; first switch means responsive to a first control signal for coupling said input node to said capacitor first plate, said first switch means being a switched-tub MOS transistor; second switch means responsive to a second control signal for coupling said capacitor first plate to said reference node; third switch means responsive to a third control signal for coupling said capacitor second plate to said reference node; fourth switch means responsive to a fourth control signal for coupling said capacitor second plate to said gain device input port, said third and fourth switch means being single MOS transistors of the same conductivity type; and clock means for providing said control signals to each of said switch means, said first and second control signals being delayed in time with respect to said third and fourth control signals such that the opening of each of said switch means coupled to said capacitor second plate occurs before the opening of each corresponding switch means not coupled thereto, whereby switching said first switch means does not produce charge injection into said gain device input port.
Claim 2
Dependent Claim
227 words
A switched capacitor circuit having an input node, an output node, and a reference node, said circuit comprising in combination: a capacitor having first and second plates; a gain device having an input port and an output port, said output port coupled to said circuit output node; first switch means responsive to a first control signal for coupling said input node to said capacitor first plate, said first switch means being a switched-tub MOS transistor; second switch means responsive to a second control signal for coupling said capacitor first plate to said reference node; third switch means responsive to a third control signal for coupling said capacitor second plate to said reference node; fourth switch means responsive to a fourth control signal for coupling said capacitor second plate to said gain device input port, said third and fourth switch means being single MOS transistors of the same conductivity type; and clock means for providing said control signals to each of said switch means, said first and second control signals being delayed in time with respect to said third and fourth control signals such that the opening of each of said switch means coupled to said capacitor second plate occurs before the opening of each corresponding switch means not coupled thereto, whereby switching said first switch means does not produce charge injection into said gain device input port.
Claim 3
Dependent Claim
49 words
The switched capacitor circuit according to claim 1, further comprising a supply node having a voltage applied thereto, and means for providing a reference voltage to said reference node, the magnitude of said reference voltage being less than one-half of the magnitude of the voltage at said supply node.
Claim 4
Dependent Claim
30 words
The switched capacitor circuit according to claim 2, wherein the magnitude of said reference voltage is approximately equal to one-third of the magnitude of the voltage at said supply node.
Claim 5
Dependent Claim
21 words
The switched capacitor circuit according to claim 1, wherein said second, third, and fourth switch means are single N-channel MOS transistors.
Claim 6
Dependent Claim
28 words
The switched capacitor circuit according to claim 1, wherein said control signals provided by said clock means for said third and fourth switch means exhibit matched fall times.
Claim 7
Dependent Claim
284 words
A switched capacitor circuit having an input node, an output node, and a reference node, said circuit comprising in combination: a first capacitor having first and second plates; a second capacitor having first and second plates; a gain device having an input port and an output port, said input port coupled to said first capacitor second plate and said second capacitor first plate, said output port coupled to said circuit output node; first switch means responsive to a first control signal for coupling said input node to said first capacitor first plate, said first switch means being a switched-tub MOS transistor; second switch means responsive to a second control signal for coupling said first capacitor first plate to said reference node; third switch means responsive to a third control signal for coupling said second capacitor second plate to said reference node; fourth switch means responsive to a fourth control signal for coupling said second capacitor second plate to said gain device output port, said fourth switch means being a switched-tub MOS transistor; fifth switch means responsive to a fifth control signal for coupling said gain device input port to said gain device output port, said fifth switch means being a single MOS transistor; and clock means for providing said control signals to each of said switch means, said first, second, third, and fourth control signals being delayed in time with respect to said fifth control signal such that the opening of each of said switch means coupled to said gain device input port occurs before the opening of each corresponding switch means not coupled thereto, whereby switching said first and fourth switch means does not produce charge injection into said gain device input port.
Claim 8
Dependent Claim
284 words
A switched capacitor circuit having an input node, an output node, and a reference node, said circuit comprising in combination: a first capacitor having first and second plates; a second capacitor having first and second plates; a gain device having an input port and an output port, said input port coupled to said first capacitor second plate and said second capacitor first plate, said output port coupled to said circuit output node; first switch means responsive to a first control signal for coupling said input node to said first capacitor first plate, said first switch means being a switched-tub MOS transistor; second switch means responsive to a second control signal for coupling said first capacitor first plate to said reference node; third switch means responsive to a third control signal for coupling said second capacitor second plate to said reference node; fourth switch means responsive to a fourth control signal for coupling said second capacitor second plate to said gain device output port, said fourth switch means being a switched-tub MOS transistor; fifth switch means responsive to a fifth control signal for coupling said gain device input port to said gain device output port, said fifth switch means being a single MOS transistor; and clock means for providing said control signals to each of said switch means, said first, second, third, and fourth control signals being delayed in time with respect to said fifth control signal such that the opening of each of said switch means coupled to said gain device input port occurs before the opening of each corresponding switch means not coupled thereto, whereby switching said first and fourth switch means does not produce charge injection into said gain device input port.
Claim 9
Dependent Claim
49 words
The switched capacitor circuit according to claim 6, further comprising a supply node having a voltage applied thereto, and means for providing a reference voltage to said reference node, the magnitude of said reference voltage being less than one-half of the magnitude of the voltage at said supply node.
Claim 10
Dependent Claim
30 words
The switched capacitor circuit according to claim 7, wherein the magnitude of said reference voltage is approximately equal to one-third of the magnitude of the voltage at said supply node.
Claim 11
Dependent Claim
21 words
The switched capacitor circuit according to claim 1, wherein said second, third, and fifth switch means are single channel MOS transistors.
References Cited (Backward Citations)
US3810031A
Cited
US3720848A
Cited
US4365204A
Cited
US4442529A
Cited
US4393351A
Cited
US4403195A
Cited
US4473761A
Cited
US4555668A
Cited
US4565971A
Cited
US4636738A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-28 | 1991-06-29 | 1991-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-28 | 1995-06-29 | 1995-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-28 | 1999-06-29 | 1999-12-29 | $7700.00 | Window Closed / Lapsed |