Semiconductor integrated circuit device and a method for manufacturing the same

Claim 2

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor layer of a predetermined conductivity type formed on a semiconductor substrate of a predetermined conductivity type; one or more first well regions of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said first well regions gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a second well region of a first conductivity type formed in contact with said first well regions at the surface of said semiconductor layer and to surround said first well regions, an impurity concentration of said second well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; one or more first buried regions of the second conductivity type formed between and adjacent to said first well regions and said semiconductor substrate, said first buried regions having a higher impurity concentration than an adjacent area of adjacent first well regions; a second buried region of the first conductivity type formed between and adjacent to said second well region and said semiconductor substrate, said second buried region having a higher impurity concentration than an adjacent area of the adjacent second well region; at least one vertical bipolar transistor formed in one of said first well regions; at least one MOS transistor of the first conductivity type formed in one of said first well regions; at least one MOS transistor of the second conductivity type formed in said second well region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective first or second well region in which said at least one MOS transistor is formed.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said semiconductor layer of said predetermined conductivity type is a semiconductor layer of the second conductivity type.

Claim 4

A semiconductor integrated circuit device according to claim 1 wherein said semiconductor layer of said predetermined conductivity type is a semiconductor layer having a substantially uniform impurity concentration distribution.

Claim 5

A semiconductor integrated circuit device according to claim 1, wherein said vertical bipolar transistor and said MOS transistor of the first conductivity type are formed in different first well regions.

Claim 6

A semiconductor integrated circuit device according to claim 1, wherein the semiconductor substrate is the first conductivity type.

Claim 7

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor layer of a predetermined conductivity type formed on a semiconductor substrate of a predetermined conductivity type; one or more first well regions of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said first well regions gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a second well region of a first conductivity type formed at a different position from that of said first well regions at the surface of said semiconductor layer, an impurity concentration of said second well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; one or more first buried regions of the second conductivity type formed between and adjacent to said first well regions and said semiconductor substrate, said first buried regions having a higher impurity concentration than an adjacent area of adjacent first well regions; a second buried region of the first conductivity type formed between and adjacent to said second well region and said semiconductor substrate and in substantial contact with said first buried region to surround said first buried region, said second buried region having a higher impurity concentration than an adjacent area of the adjacent second well region; at least one vertical bipolar transistor formed in one of said first well regions; at least one MOS transistor of the first conductivity type formed in one of said first well regions; at least one mOS transistor of the second conductivity type formed in said second well region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective first or second well region in which said at least one MOS transistor is formed.

Claim 8

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor layer of a predetermined conductivity type formed on a semiconductor substrate of a predetermined conductivity type; one or more first well regions of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said first well regions gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a second well region of a first conductivity type formed at a different position from that of said first well regions at the surface of said semiconductor layer, an impurity concentration of said second well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; one or more first buried regions of the second conductivity type formed between and adjacent to said first well regions and said semiconductor substrate, said first buried regions having a higher impurity concentration than an adjacent area of adjacent first well regions; a second buried region of the first conductivity type formed between and adjacent to said second well region and said semiconductor substrate and in substantial contact with said first buried region to surround said first buried region, said second buried region having a higher impurity concentration than an adjacent area of the adjacent second well region; at least one vertical bipolar transistor formed in one of said first well regions; at least one MOS transistor of the first conductivity type formed in one of said first well regions; at least one mOS transistor of the second conductivity type formed in said second well region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective first or second well region in which said at least one MOS transistor is formed.

Claim 9

A semiconductor integrated circuit device according to claim 6, wherein said semiconductor layer of said predetermined conductivity type is a semiconductor layer of the second conductivity type.

Claim 10

A semiconductor integrated circuit device according to claim 6, wherein said semiconductor layer of said predetermined conductivity type is a semiconductor layer having a substantially uniform impurity concentration distribution.

Claim 11

A semiconductor integrated circuit device according to claim 6, wherein said second well region is formed in contact with said first well region to surround said first well region.

Claim 12

A semiconductor integrated circuit device according to claim 9, wherein a boundary plane of said first well region and said second well region and a boundary plane of said first buried region and said second buried region are in substantially the same plane.

Claim 13

A semiconductor integrated circuit device according to claim 6, wherein said vertical bipolar transistor and said MOS transistor of the first conductivity type are formed in different first well regions.

Claim 14

A semiconductor integrated circuit device according to claim 6, wherein the semiconductor substrate is the first conductivity type.

Claim 15

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor substrate of a predetermined conductivity type; one or more first regions of a second conductivity type formed at a predetermined position above a first surface of said semiconductor substrate, an impurity concentration of said first regions gradually decreasing as it goes from a first surface of said first regions toward said first surface of said semiconductor substrate; a second region of a first conductivity type formed at a different position from that of said first regions above the first surface of said semiconductor substrate, an impurity concentration of said second region gradually decreasing as it goes from a first surface of said second region toward said first surface of said semiconductor substrate; one or more third regions of the second conductivity type formed between and adjacent to said first regions and said first surface of said semiconductor substrate, said third regions having a higher impurity concentration than an adjacent area of adjacent first regions; a fourth region of the first conductivity type formed between and adjacent to said second region and said first surface of said semiconductor substrate, said fourth region having a higher impurity concentration than an adjacent area of the adjacent second region; at least one vertical bipolar transistor formed in one of said first regions; at least one MOS transistor of the first conductivity type formed in one of said first regions; at least one MOS transistor of the second conductivity type formed in said second region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective first or second region in which said at least one MOS transistor is formed.

Claim 16

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor substrate of a predetermined conductivity type; one or more first regions of a second conductivity type formed at a predetermined position above a first surface of said semiconductor substrate, an impurity concentration of said first regions gradually decreasing as it goes from a first surface of said first regions toward said first surface of said semiconductor substrate; a second region of a first conductivity type formed at a different position from that of said first regions above the first surface of said semiconductor substrate, an impurity concentration of said second region gradually decreasing as it goes from a first surface of said second region toward said first surface of said semiconductor substrate; one or more third regions of the second conductivity type formed between and adjacent to said first regions and said first surface of said semiconductor substrate, said third regions having a higher impurity concentration than an adjacent area of adjacent first regions; a fourth region of the first conductivity type formed between and adjacent to said second region and said first surface of said semiconductor substrate, said fourth region having a higher impurity concentration than an adjacent area of the adjacent second region; at least one vertical bipolar transistor formed in one of said first regions; at least one MOS transistor of the first conductivity type formed in one of said first regions; at least one MOS transistor of the second conductivity type formed in said second region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective first or second region in which said at least one MOS transistor is formed.

Claim 17

A semiconductor integrated circuit device according to claim 13, wherein said second region is in contact with and surrounds said at least one first region above the first surface of said substrate.

Claim 18

A semiconductor integrated circuit device according to claim 13 wherein said fourth region is in contact with and surrounds said third region adjacent to said first surface of said substrate.

Claim 19

A semiconductor integrated circuit device according to claim 13, wherein said vertical bipolar transistor and said MOS transistor of the first conductivity type are formed in different first regions.

Claim 20

A semiconductor integrated circuit device according to claim 13, wherein the semiconductor substrate is the first conductivity type.

Claim 21

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor substrate of a predetermined conductivity type; a first region of a second conductivity type formed at a predetermined position above a first surface of said semiconductor substrate, an impurity concentration of said first region gradually decreasing as it goes from a first surface of said first region toward said first surface of said semiconductor substrate; a second region of a first condcutvity type formed at a different position from that of said first region above the first surface of said semiconductor substrate, an impurity concentration of said second region gradually decreasing as it goes from a first surface of said second region toward said first surface of said semiconductor substrate; a third region of the second conductivity type formed between and adjacent to said first region and said first surface of said semiconductor substrate, said third region having a higher impurity concentration than an adjacent area of the adjacent first region; a fourth region of the first conductivity type formed between and adjacent to said second region and said first surface of said semiconductor substrate, said fourth region having a higher impurity concentration than an adjacent area of the adjacent second region; a fifth region of the second conductivity type formed at a different position from that of either said first or second regions above said first surface of said semiconductor substrate, an impurity concentration of said fifth region gradually decreasing as it goes from a first surface of said fifth region toward said first surface of said semiconductor substrate; a sixth region of the second conductivity type formed between and adjacent to said fifth region and said first surface of said semiconductor substrate, said sixth region having a higher impurity concentration than an adjacent area of the adjacent fifth region; at least one vertical bipolar transistor formed in said first region; at least one MOS transistor of the first conductivity type formed in said fifth region; at least one MOS transistor of the second conductivity type formed in said second region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective second or fifth region in which said at least one MOS transistor is formed.

Claim 22

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor substrate of a predetermined conductivity type; a first region of a second conductivity type formed at a predetermined position above a first surface of said semiconductor substrate, an impurity concentration of said first region gradually decreasing as it goes from a first surface of said first region toward said first surface of said semiconductor substrate; a second region of a first condcutvity type formed at a different position from that of said first region above the first surface of said semiconductor substrate, an impurity concentration of said second region gradually decreasing as it goes from a first surface of said second region toward said first surface of said semiconductor substrate; a third region of the second conductivity type formed between and adjacent to said first region and said first surface of said semiconductor substrate, said third region having a higher impurity concentration than an adjacent area of the adjacent first region; a fourth region of the first conductivity type formed between and adjacent to said second region and said first surface of said semiconductor substrate, said fourth region having a higher impurity concentration than an adjacent area of the adjacent second region; a fifth region of the second conductivity type formed at a different position from that of either said first or second regions above said first surface of said semiconductor substrate, an impurity concentration of said fifth region gradually decreasing as it goes from a first surface of said fifth region toward said first surface of said semiconductor substrate; a sixth region of the second conductivity type formed between and adjacent to said fifth region and said first surface of said semiconductor substrate, said sixth region having a higher impurity concentration than an adjacent area of the adjacent fifth region; at least one vertical bipolar transistor formed in said first region; at least one MOS transistor of the first conductivity type formed in said fifth region; at least one MOS transistor of the second conductivity type formed in said second region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective second or fifth region in which said at least one MOS transistor is formed.

Claim 23

A semiconductor integrated circuit device according to claim 18, wherein said second region is in contact with and surrounds said first region above the first surface of said substrate.

Claim 24

A semiconductor integrated circuit device according to claim 18 wherein said fourth region is in contact with and surrounds said third region adjacent to said first surface of said substrate.

Claim 25

A semiconductor integrated circuit device according to claim 18, wherein the semiconductor substrate is the first conductivity type.

Claim 26

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor layer of a predetermined conductivity type formed on a semiconductor substrate of a predetermined conductivity type; a first well region of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said first well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a second well region of a first conductivity type formed in contact with said first well region at the surface of said semiconductor layer and to surround said first well region, an impurity concentration of said second well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a first buried region of the second conductivity type formed between and adjacent to said first well region and said semiconductor substrate, said first buried region having a higher impurity concentration than an adjacent area of the adjacent first well region; a second buried region of the first conductivity type formed between and adjacent to said second well region and said semiconductor substrate, said second buried region having a higher impurity concentration than an adjacent area of the adjacent second well region; a third well region of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said third well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a third buried region of the second conductivity type formed between and adjacent to said third well region and said semiconductor substrate, said third buried region having a higher impurity concentration than an adjacent area of the adjacent third well region; at least one vertical bipolar transistor formed in said first well region; at least one MOS transistor of the first conductivity type formed in said third well region; at least one MOS transistor of the second conductivity type formed in said second well region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective second or third well region in which said at least one MOS transistor is formed.

Claim 27

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor layer of a predetermined conductivity type formed on a semiconductor substrate of a predetermined conductivity type; a first well region of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said first well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a second well region of a first conductivity type formed in contact with said first well region at the surface of said semiconductor layer and to surround said first well region, an impurity concentration of said second well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a first buried region of the second conductivity type formed between and adjacent to said first well region and said semiconductor substrate, said first buried region having a higher impurity concentration than an adjacent area of the adjacent first well region; a second buried region of the first conductivity type formed between and adjacent to said second well region and said semiconductor substrate, said second buried region having a higher impurity concentration than an adjacent area of the adjacent second well region; a third well region of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said third well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a third buried region of the second conductivity type formed between and adjacent to said third well region and said semiconductor substrate, said third buried region having a higher impurity concentration than an adjacent area of the adjacent third well region; at least one vertical bipolar transistor formed in said first well region; at least one MOS transistor of the first conductivity type formed in said third well region; at least one MOS transistor of the second conductivity type formed in said second well region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective second or third well region in which said at least one MOS transistor is formed.

Claim 28

A semiconductor integrated circuit device according to claim 22 wherein said semiconductor layer of said predetermined conductivity type is a semiconductor layer of the second conductivity type.

Claim 29

A semiconductor integrated circuit device according to claim 22, wherein said semiconductor layer of said predetermined conductivity type is a semiconductor layer having a substantially uniform impurity concentration distribution.

Claim 30

A semiconductor integrated circuit device according to claim 22, wherein the semiconductor substrate is the first conductivity type.

Claim 31

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor layer of a predetermined conductivity type formed on a semiconductor substrate of a predetermined conductivity type; a first well region of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said first well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a second well region of a first conductivity type formed at a different position from that of said first well region at the surface of said semiconductor, an impurity concentration of said second well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a first buried region of the second conductivity type formed between and adjacent to said first well region and said semiconductor substrate, said first buried region having a higher impurity concentration than an adjacent area of the adjacent first well region; a second buried region of the first conductivity type formed between and adjacent to said second well region and said semiconductor substrate and in substantial contact with said first buried region to surround said first buried region, said second buried region having a higher impurity concentration than an adjacent area of the adjacent second well region; a third well region of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said third well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a third buried region of the second conductivity type formed between and adjacent to said third well region and said semiconductor substrate, said third buried region having a higher impurity concentration than an adjacent area of the adjacent third well region; at least one vertical bipolar transistor formed in said first well region; at least one MOS transistor of the first conductivity type formed in said third well region; at least one MOS transistor of the second conductivity type formed in said second well region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective second or third well region in which said at least one MOS transistor is formed.

Claim 32

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor layer of a predetermined conductivity type formed on a semiconductor substrate of a predetermined conductivity type; a first well region of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said first well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a second well region of a first conductivity type formed at a different position from that of said first well region at the surface of said semiconductor, an impurity concentration of said second well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a first buried region of the second conductivity type formed between and adjacent to said first well region and said semiconductor substrate, said first buried region having a higher impurity concentration than an adjacent area of the adjacent first well region; a second buried region of the first conductivity type formed between and adjacent to said second well region and said semiconductor substrate and in substantial contact with said first buried region to surround said first buried region, said second buried region having a higher impurity concentration than an adjacent area of the adjacent second well region; a third well region of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said third well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a third buried region of the second conductivity type formed between and adjacent to said third well region and said semiconductor substrate, said third buried region having a higher impurity concentration than an adjacent area of the adjacent third well region; at least one vertical bipolar transistor formed in said first well region; at least one MOS transistor of the first conductivity type formed in said third well region; at least one MOS transistor of the second conductivity type formed in said second well region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective second or third well region in which said at least one MOS transistor is formed.

Claim 33

A semiconductor integrated circuit device according to claim 26, wherein said second well region is formed in contact with said first well region to surround said first well region.

Claim 34

A semiconductor integrated circuit device according to claim 26 wherein said semiconductor layer of said predetermined conductivity type is a semiconductor layer of the second conductivity type.

Claim 35

A semiconductor integrated circuit device according to claim 26 wherein said semiconductor layer of said predetermined conductivity type is a semiconductor layer having a substantially uniform impurity concentration distribution.

Claim 36

A semiconductor integrated circuit device according to claim 27, wherein a boundary plane of said first well region and said second well region and a boundary plane of said first buried region and said second buried region are in substantially the same plane.

Claim 37

A semiconductor integrated circuit device according to claim 26, wherein the semiconductor substrate is the first conductivity type.

Claim 38

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor substrate having a first and a second surface; a substrate region of a predetermined conductivity type formed at a predetermined position of the second surface; one o more first regions of a second conductivity type formed at a predetermined position above the first surface of said semiconductor substrate, an impurity concentration of said first regions gradually decreasing as it goes from the first surface of said semiconductor substrate toward the second surface of said semiconductor substrate; a second region of a first conductivity type formed at a different position of the first surface of said semiconductor substrate from that of said first regions, an impurity concentration of said second region gradually decreasing as it goes from the first surface of said semiconductor substrate toward the second surface of said semiconductor substrate; one or more third regions of the second conductivity type formed between and adjacent to said first regions and said substrate region, said third regions having a higher impurity concentration than an adjacent area of adjacent first regions; a fourth region of the first conductivity type formed between and adjacent to said second region and said substrate region, said fourth region having a higher impurity concentration than an adjacent area of the adjacent second region; a vertical bipolar transistor formed in one of said first regions; a MOS transistor of the first condcutvity type formed in one of said first regions; a MOS transistor of the second conductivity type formed in said second region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective first or second region in which said at least one MOS transistor is formed.

Claim 39

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor substrate having a first and a second surface; a substrate region of a predetermined conductivity type formed at a predetermined position of the second surface; one o more first regions of a second conductivity type formed at a predetermined position above the first surface of said semiconductor substrate, an impurity concentration of said first regions gradually decreasing as it goes from the first surface of said semiconductor substrate toward the second surface of said semiconductor substrate; a second region of a first conductivity type formed at a different position of the first surface of said semiconductor substrate from that of said first regions, an impurity concentration of said second region gradually decreasing as it goes from the first surface of said semiconductor substrate toward the second surface of said semiconductor substrate; one or more third regions of the second conductivity type formed between and adjacent to said first regions and said substrate region, said third regions having a higher impurity concentration than an adjacent area of adjacent first regions; a fourth region of the first conductivity type formed between and adjacent to said second region and said substrate region, said fourth region having a higher impurity concentration than an adjacent area of the adjacent second region; a vertical bipolar transistor formed in one of said first regions; a MOS transistor of the first condcutvity type formed in one of said first regions; a MOS transistor of the second conductivity type formed in said second region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective first or second region in which said at least one MOS transistor is formed.

Claim 40

A semiconductor integrated circuit device according to claim 32, wherein said vertical bipolar transistor and said MOS transistor of the first conductivity type are formed in different first regions.

Claim 41

A semiconductor integrated circuit device according to claim 32, wherein the semiconductor substrate is the first conductivity type.

Claim 42

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor substrate having a first and a second surface; a substrate region of a predetermined conductivity type formed at a predetermined position of the second surface; a first region of a second conductivity type formed at a predetermined position of the first surface of said semiconductor substrate, an impurity concentration of said first region gradually decreasing as it goes from the first surface of said semiconductor substrate toward the second surface of said semiconductor substrate; a second region of a first conductivity type formed at a different position of the first surface of said semiconductor substrate from that of said first region, an impurity concentration of said second region gradually decreasing as it goes from the first surface of said semiconductor substrate toward the second surface of said semiconductor substrate; a third region of the second conductivity type formed between and adjacent to said first region and said substrate region, said third region having a higher impurity concentration than an adjacent area of the adjacent first region; a fourth region of the first conductivity type formed between and adjacent to said second region and said substrate region, said fourth region having a higher impurity concentration than an adjacent area of the adjacent second region; a fifth region of the second conductivity type formed at a different position of the first surface of said semiconductor substrate from that of either said first or second region, an impurity concentration of said first region gradually decreasing as it goes from the first surface of said semiconductor substrate toward the second surface of said semiconductor substrate; a sixth region of the second conductivity type formed between and adjacent to said fifth region and said substrate region, said sixth region having a higher impurity concentration than an adjacent area of the adjacent fifth region; a vertical bipolar transistor formed in said first region; a MOS transistor of the first conductivity type formed in said fifth region; a MOS transistor of the second conductivity type formed in said second region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective second or fifth region in which said at least one MOS transistor is formed.

Claim 43

A semiconductor integrated circuit device having a bipolar transistor and complementary MOS transistors, comprising: a semiconductor substrate having a first and a second surface; a substrate region of a predetermined conductivity type formed at a predetermined position of the second surface; a first region of a second conductivity type formed at a predetermined position of the first surface of said semiconductor substrate, an impurity concentration of said first region gradually decreasing as it goes from the first surface of said semiconductor substrate toward the second surface of said semiconductor substrate; a second region of a first conductivity type formed at a different position of the first surface of said semiconductor substrate from that of said first region, an impurity concentration of said second region gradually decreasing as it goes from the first surface of said semiconductor substrate toward the second surface of said semiconductor substrate; a third region of the second conductivity type formed between and adjacent to said first region and said substrate region, said third region having a higher impurity concentration than an adjacent area of the adjacent first region; a fourth region of the first conductivity type formed between and adjacent to said second region and said substrate region, said fourth region having a higher impurity concentration than an adjacent area of the adjacent second region; a fifth region of the second conductivity type formed at a different position of the first surface of said semiconductor substrate from that of either said first or second region, an impurity concentration of said first region gradually decreasing as it goes from the first surface of said semiconductor substrate toward the second surface of said semiconductor substrate; a sixth region of the second conductivity type formed between and adjacent to said fifth region and said substrate region, said sixth region having a higher impurity concentration than an adjacent area of the adjacent fifth region; a vertical bipolar transistor formed in said first region; a MOS transistor of the first conductivity type formed in said fifth region; a MOS transistor of the second conductivity type formed in said second region; and means for applying a relative bias between the source of at least one of said MOS transistors of the first conductivity type or the second conductivity type and the respective second or fifth region in which said at least one MOS transistor is formed.

Claim 44

A semiconductor integrated circuit device according to claim 35, wherein the semiconductor substrate is the first conductivity type.