US4980738A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single polysilicon layer transistor with reduced emitter and base resistance
Assignee: Texas Instruments Inc
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Filing: 1988-06-29
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Granted: 1990-12-25
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Expires: 2008-06-29
Abstract
Abstract A single layer polysilicon self-aligned transistor (52) is provided having a substantially vertical emitter contact region (62), such that the emitter contact region (62) does not require extending portions overlying the base region (60). Heavily doped silicided regions (68) are disposed adjacent the emitter (64) in a self-aligned process such that the base resistance of the device is minimized. A planar oxide layer (72) is formed such that the emitter contact region (62) are exposed without exposing other polysilicon gates of the integrated circuit. A metal layer (76) may be disposed over the planar oxide layer (72) to form a level of interconnects.
Inventors
- 👤 Michael T. Welch
- 👤 David P. Favreau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:40
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/27; H10D64/281; H10D64/23; H10D64/231
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
154 words
A transistor, comprising: a semiconductor surface of a first conductivity type; dielectric regions overlying said semiconductor surface, the dielectric regions defining a base region in the semiconductor surface; a base region of a second conductivity type formed between the dielectric regions; an emitter contact region comprising a polysilicon region overlying a portion of said base region, the emitter contact region having substantially vertical sidewalls extending upward from the surface of the base region; dielectric sidewalls on the emitter contact region; an emitter region of the first conductivity type formed in the base region, the emitter region being formed in alignment with the sidewalls of the emitter contact region; silicided regions formed on the exposed portions of the base region and the emitter contact region, the silicided regions on the base region being formed in alignment with the dielectric sidewalls; and a dielectric layer overlying the base region substantially planar with the emitter contact region.
Claim 2
Dependent Claim
154 words
A transistor, comprising: a semiconductor surface of a first conductivity type; dielectric regions overlying said semiconductor surface, the dielectric regions defining a base region in the semiconductor surface; a base region of a second conductivity type formed between the dielectric regions; an emitter contact region comprising a polysilicon region overlying a portion of said base region, the emitter contact region having substantially vertical sidewalls extending upward from the surface of the base region; dielectric sidewalls on the emitter contact region; an emitter region of the first conductivity type formed in the base region, the emitter region being formed in alignment with the sidewalls of the emitter contact region; silicided regions formed on the exposed portions of the base region and the emitter contact region, the silicided regions on the base region being formed in alignment with the dielectric sidewalls; and a dielectric layer overlying the base region substantially planar with the emitter contact region.
Claim 3
Dependent Claim
32 words
The transistor of claim 1, further comprising: a metal contact formed over a portion of the silicided regions formed on the base region, the metal contact being disposed beneath the dielectric layer.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-24 | 1994-06-25 | 1994-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-24 | 1998-06-25 | 1998-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-24 | 2002-06-25 | 2002-12-25 | $7700.00 | Window Closed / Lapsed |