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US4980585A
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Method and apparatus for synthesizing digital waveforms
Assignee: Intel Corp
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Filing: 1989-12-01
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Granted: 1990-12-25
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Expires: 2009-12-01
Abstract
Abstract An integrated circuit apparatus for performing digital synthesis of regular waveforms having transitions at arbitrary points in time is disclosed. A reference clock signal is provided as input to a synchronous delay line apparatus, producing a plurality of taps. The taps signal provides N inputs to a digital-to-time domain converter (DTC), where N is the resolution of the synthesized waveform, said DTC apparatus further receiving inputs from a pattern generator apparatus over a shifter apparatus and a pattern register apparatus. The DTC apparatus combines the taps signal and the input from said pattern register to produce a synthesized waveform. In the presently preferred embodiment, the DTC apparatus comprises a plurality of pairs of N-type and P-type devices connected as transmission gates. When the transmission gate is turned on, it transfers the input pattern bits to the output line. When the transmission gate is turned off, it effectively has an infinite impedance and isolates the input pattern from the output line. Only one transmission gate in the DTC apparatus is turned on at one time. The waveform pattern register apparatus has varying depths of master and slave latches. It receives pattern inputs from the pattern generator apparatus and outputs in three separate fields to the DTC apparatus. The bits of the first field of the pattern waveform register are implemented as a solitary master stage. The bits of the second field of the waveform pattern register are implemented as complete master-slave pairs. The bits of the third field of the waveform pattern register are implemented as master-slave-master triads.
Inventors
- 👤 Mel Bazes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:39
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/02; G06F1/025; H; H04; H04M; H04M1/00; H04M1/26; H04M1/30; H04M1/50; H04M1/505
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
95 words
An integrated circuit for synthesizing a digital waveform having a plurality of frequencies with respect to a reference signal, comprising: a synchronous delay line for generating a plurality of taps in response to receiving said reference signal; a digital-to-time domain converter connected to said synchronous delay line for generating said digital waveform from said plurality of taps; a waveform pattern register connected to said digital-to-time domain converter for synchronizing the synthesis of said digital waveform by said digital-to-time domain converter: and a pattern generator connected to said waveform pattern register for generating a waveform pattern.
Claim 2
Dependent Claim
95 words
An integrated circuit for synthesizing a digital waveform having a plurality of frequencies with respect to a reference signal, comprising: a synchronous delay line for generating a plurality of taps in response to receiving said reference signal; a digital-to-time domain converter connected to said synchronous delay line for generating said digital waveform from said plurality of taps; a waveform pattern register connected to said digital-to-time domain converter for synchronizing the synthesis of said digital waveform by said digital-to-time domain converter: and a pattern generator connected to said waveform pattern register for generating a waveform pattern.
Claim 3
Dependent Claim
25 words
The apparatus as defined in claim 1, wherein the multiplication of the frequency of said reference signal and that of said digital waveform is N.
Claim 4
Dependent Claim
13 words
The apparatus as defined in claim 2 wherein said N is an integer.
Claim 5
Dependent Claim
14 words
The apparatus as defined in claim 3 wherein said N is a rational number.
Claim 6
Dependent Claim
30 words
The apparatus as defined in claim 1, wherein said reference signal having a frequency that is different by a predetermined integer or rational number with that of said digital waveform.
Claim 7
Dependent Claim
14 words
The apparatus as defined in claim 5, wherein said synthesized waveform is pseudo random.
Claim 8
Dependent Claim
24 words
The apparatus as defined in claim 1 wherein said digital-to-time domain converter comprises a plurality of transmission gates coupled to a common output line.
Claim 9
Dependent Claim
18 words
The apparatus as defined in claim 1, wherein said waveform register comprses fields of master and slave flip-flops.
Claim 10
Dependent Claim
41 words
The waveform register as defined in claim 8, wherein fields of master and slave flip-flops further comprise three fields, said first comprising master flip-flops, said second field comprising pairs of master and slave flip-flops, and said third field comprising master-slave-master triads.
Claim 11
Dependent Claim
14 words
The apparatus as defined in claim 1, wherein said pattern generator compriese hard-wired pattern.
Claim 12
Dependent Claim
14 words
The apparatus as defined in claim 1, wherein said pattern generator comprises RAM/ROM arrays.
Claim 13
Dependent Claim
16 words
The apparatus as defined in claim 1, wherein said pattern generator comprises real time pattern generator.
Claim 14
Dependent Claim
107 words
An integrated circuit for generating a digital waveform having a plurality of frequencies with respect to a reference signal, comprising: a synchronous delay line for generating a plurality of taps in response to receiving said reference signal; a digital-to-time domain converter connected to said synchronous delay line for synthesizing said digital waveform from said plurality of taps; a waveform pattern register connected to said digital-to-time domain converter for sycnchronizing the synthesis of said digital waveform by said digital-to-time domain converter; a shifter connected to said waveform pattern register for shifting the position of pattern; and a pattern generator connected to said waveform pattern register for generating waveform.
Claim 15
Dependent Claim
107 words
An integrated circuit for generating a digital waveform having a plurality of frequencies with respect to a reference signal, comprising: a synchronous delay line for generating a plurality of taps in response to receiving said reference signal; a digital-to-time domain converter connected to said synchronous delay line for synthesizing said digital waveform from said plurality of taps; a waveform pattern register connected to said digital-to-time domain converter for sycnchronizing the synthesis of said digital waveform by said digital-to-time domain converter; a shifter connected to said waveform pattern register for shifting the position of pattern; and a pattern generator connected to said waveform pattern register for generating waveform.
Claim 16
Dependent Claim
25 words
The apparatus as defined in claim 13 wherein the multiplication of the frequency of said reference signal and that of said digital waveform is N.
Claim 17
Dependent Claim
13 words
The apparatus as defined n claim 14, wherein said N is an integer.
Claim 18
Dependent Claim
14 words
The apparatus as defined in claim 15, wherein said N is a rational number.
Claim 19
Dependent Claim
30 words
The apparatus as defined in claim 13, wherein said reference signal has a frequency that is differnt by a predetermined integer or rational number with that of said digital waveform.
Claim 20
Dependent Claim
14 words
The apparatus as defined in claim 17, wherein said synthesized waveform is pseudo random.
Claim 21
Dependent Claim
37 words
The apparatus as defined in claim 13, wherein said digital-to-time domain converter comprises a plurality fo transmission gates coupled to a common output line, each said transmission gates further comprising a pair of N and P devices.
Claim 22
Dependent Claim
18 words
The apparatus as defined in claim 13, wherein said waveform register comprises fields of master and slave flip-flops.
Claim 23
Dependent Claim
42 words
The waveform register as defined in claim 20, wherein fields of naster and slave flip-flops further comprise three fields, said first field comprising master flip-flops, said second field comprising pairs of master and slave flip-flops, and said third field comprising master-slave-master triads.
Claim 24
Dependent Claim
14 words
The apparatus as defined in claim 13, wherein said pattern generator comprises hard-wired pattern.
Claim 25
Dependent Claim
14 words
The apparatus as defined in claim 13, wherein said pattern generator comprises RAM/ROM arrays.
Claim 26
Dependent Claim
16 words
The apparatus as defined in claim 13, wherein said pattern generator comprises real time pattern generator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-24 | 1994-06-25 | 1994-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-24 | 1998-06-25 | 1998-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-24 | 2002-06-25 | 2002-12-25 | $7700.00 | Window Closed / Lapsed |