US4980317A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of producing integrated semiconductor structures comprising field-effect transistors with channel lengths in the submicron range using a three-layer resist system
Assignee: International Business Machines Corp
•
Filing: 1989-03-21
•
Granted: 1990-12-25
•
Expires: 2009-03-21
Abstract
Abstract Disclosed is a method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, wherein a three-layer resist system is used to produce a polymer or resist mask. The polymer or resist mask thus produced is used to etch a layer of polysilicon on the semiconductor substrate. The method is characterized in that the pattern, produced conventionally in the top layer of the three-layer resist and including an angle < about 90 DEG , is transferred by RIE, using CF4, to the center layer of plasma nitride and by RIE, using oxygen, to the bottom resist or polymer layer. In a prior art method, this was followed by lateral etching in oxygen to reduce the dimensions of the mask by a desired amount. The improved method of the invention provides for the plasma nitride mask to be removed first, using, if necessary a facetting step in oxygen to increase the positive angle in the mask structure, and then for the latter structure to be laterally etched in oxygen to reduce its dimensions by the desired amount. As the angle in the mask is < about 90 DEG , the parameters for lateral etching may be chosen such that the etch process is largely anisotropic and, thus, accurately and readily determinable. As a result, the absolute amount of lateral etching may be accurately adjusted during the etch period. As shading plasma nitride is removed before lateral etching, the influence of neighboring structures on lateral etching is largely reduced. The mask thus produced is used to etch in the polysilicon layer structures whose angles ensure a good definition of the spacers to be produced in the subsequent process steps and of ion implantation, which both determine the effective channel length of field-effect transistors.
Inventors
- 👤 Otto Koblinger
- 👤 Reinhold Muhl
- 👤 Hans-Joachim Trumpp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:18
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/20; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; Y; Y10; Y10S; Y10S148/00; Y10S148/051; Y10S148/137; Y10S438/00; Y10S438/942; Y10S438/947; Y10S438/948; Y10S438/95; Y10S438/97
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
236 words
A method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, comprising: (a) depositing three layers on a semiconductor substrate, the bottom layer being of a photoresist or polymer material and in contact with the upper surface of said substrate, the intermediate layer being of silicon nitride and in contact with the upper surface of said bottom layer, and the upper layer being of a highly sensitive photoresist and in contact with the upper surface of said intermediate layer; (b) generating a desired mask pattern in said upper layer and transferring the pattern by RIE or plasma etching to said silicon nitride layer; (c) transferring the pattern to said photoresist or polymer layer by RIE, using oxygen, said silicon nitride layer serving as a mask; (d) removing said patterned silicon nitride layer by RIE or plasma etching; (e) laterally etching, after removal of said silicon nitride layer, to reduce the dimensions of the resulting mask in said photoresist or polymer layer by a desired amount, said lateral etching being substantially anisotropic and controllable as a function of time and with O 2 at a gas flow of about 80 to about 120 sccm, a pressure of about 90 to about 100 μbar, and an energy density of about 0.2 to about 0.4 Watt/cm 2 ; and (f) etching said semiconductor substrate using the resulting mask in said photoresist or polymer layer.
Claim 2
Independent Claim
236 words
A method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, comprising: (a) depositing three layers on a semiconductor substrate, the bottom layer being of a photoresist or polymer material and in contact with the upper surface of said substrate, the intermediate layer being of silicon nitride and in contact with the upper surface of said bottom layer, and the upper layer being of a highly sensitive photoresist and in contact with the upper surface of said intermediate layer; (b) generating a desired mask pattern in said upper layer and transferring the pattern by RIE or plasma etching to said silicon nitride layer; (c) transferring the pattern to said photoresist or polymer layer by RIE, using oxygen, said silicon nitride layer serving as a mask; (d) removing said patterned silicon nitride layer by RIE or plasma etching; (e) laterally etching, after removal of said silicon nitride layer, to reduce the dimensions of the resulting mask in said photoresist or polymer layer by a desired amount, said lateral etching being substantially anisotropic and controllable as a function of time and with O 2 at a gas flow of about 80 to about 120 sccm, a pressure of about 90 to about 100 μbar, and an energy density of about 0.2 to about 0.4 Watt/cm 2 ; and (f) etching said semiconductor substrate using the resulting mask in said photoresist or polymer layer.
Claim 3
Dependent Claim
28 words
The method of claim 1, wherein, before the resulting mask in said photoresist or polymer layer is laterally etched, it is subjected to a facetting step in oxygen.
Claim 4
Dependent Claim
16 words
The method of claim 1, wherein the RIE steps are carried out in the same equipment.
Claim 5
Dependent Claim
21 words
The method of claim 3, wherein the RIE steps are carried out in a parallel plate reactor or in a hexode.
Claim 6
Dependent Claim
49 words
The method of claim 1, wherein said silicon nitride layer is etched with CF 4 , using a gas flow of about 20 to about 50 sccm, a pressure of about 30 to about 60 μbar and an energy density of about 0.3 to about 0.5 Watt/cm 2 .
Claim 7
Dependent Claim
40 words
The method of claim 1, wherein said photoresist or polymer layer is etched with oxygen at a pressure of < about 12 μbar, yielding angles of about 80° to about 85° in the mask in said photoresist or polymer layer.
Claim 8
Dependent Claim
51 words
The method of claim 6, wherein said photoresist or polymer layer is anisotropically etched with O 2 , using a gas flow of about 40 to about 60 sccm, a pressure of about 8 to about 12 μbar, and an energy density of about 0.2 to about 0.4 Watt/cm 2 .
Claim 9
Dependent Claim
58 words
The method of claim 7, wherein for increasing the positive angle, the mask in said photoresist or polymer layer is subjected to a facetting step in oxygen, using a gas flow of about 15 to about 25 sccm, a pressure of < about 1 μbar, and an energy density of about 0.2 to about 0.4 Watt/cm 2 .
Claim 10
Dependent Claim
44 words
The method of claim 1, wherein after removal of said silicon nitride layer, the mask in said photoresist or polymer layer is laterally etched at an oxygen pressure of about 100 μbar for a predetermined time to reduce its dimensions by a predetermined amount.
Claim 11
Dependent Claim
29 words
The method of claim 1, wherein the mask in said photoresist or polymer layer is used to etch a structure with angles < about 90° into said semiconductor substrate.
Claim 12
Dependent Claim
47 words
The method of claim 10, wherein said substrate comprises polysilicon, and further wherein a mixture, in volume per cent, of about 6 to about 8% SF 6 , about 2 to about 3% Cl 2 , with the remainder helium, is used to RIE etch said substrate.
Claim 13
Dependent Claim
34 words
The method of claim 1, wherein said bottom layer is based on a phenolic resin and a diester of a 1-oxo-2-diazonaphthalene sulfonic acid with an unsymmetrical primary or secondary alphatic diol as a sensitizer.
Claim 14
Dependent Claim
18 words
The method of claim 12, wherein said upper layer is of the same material as said bottom layer.
Claim 15
Dependent Claim
37 words
The method of claim 13, wherein said bottom layer has a thickness of about 1.1 μm, said intermediate layer has a thickness of about 0.1 μm and said upper layer has a thickness of about 0.8 μm.
Claim 16
Independent Claim
273 words
A method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, comprising: (a) depositing three layers on a semiconductor substrate, the bottom layer being of a photoresist or polymer material and in contact with the upper surface of said substrate, the intermediate layer being of silicon nitride and in contact with the upper surface of said bottom layer, and the upper layer being of a highly sensitive photoresist and in contact with the upper surface of said intermediate layer; (b) generating a desired mask pattern in said upper layer and transferring the pattern by RIE or plasma etching to said silicon nitride layer with CF 4 , using a gas flow of about 20 to about 50 sccm, a pressure of about 30 to about 60 μbar, and an energy density of about 0.3 to about 0.5 Watt/cm 2 ; (c) transferring the pattern to said photoresist or polymer layer by RIE, using oxygen, said silicon nitride layer serving as a mask; (d) removing said patterned silicon nitride layer by RIE or plasma etching with CF 4 , using a gas flow of about 20 to about 50 sccm, a pressure of about 30 to about 60 μbar, and an energy density of about 0.3 to about 0.5 Watt/cm 2 ; (e) laterally etching, after removal of said silicon nitride layer, to reduce the dimensions of the resulting mask in said photoresist or polymer layer by a desired amount, said lateral etching being substantially anisotropic and controllable as a function of time; and (f) etching said semiconductor substrate using the resulting mask in said photoresist or polymer layer.
Claim 17
Independent Claim
273 words
A method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, comprising: (a) depositing three layers on a semiconductor substrate, the bottom layer being of a photoresist or polymer material and in contact with the upper surface of said substrate, the intermediate layer being of silicon nitride and in contact with the upper surface of said bottom layer, and the upper layer being of a highly sensitive photoresist and in contact with the upper surface of said intermediate layer; (b) generating a desired mask pattern in said upper layer and transferring the pattern by RIE or plasma etching to said silicon nitride layer with CF 4 , using a gas flow of about 20 to about 50 sccm, a pressure of about 30 to about 60 μbar, and an energy density of about 0.3 to about 0.5 Watt/cm 2 ; (c) transferring the pattern to said photoresist or polymer layer by RIE, using oxygen, said silicon nitride layer serving as a mask; (d) removing said patterned silicon nitride layer by RIE or plasma etching with CF 4 , using a gas flow of about 20 to about 50 sccm, a pressure of about 30 to about 60 μbar, and an energy density of about 0.3 to about 0.5 Watt/cm 2 ; (e) laterally etching, after removal of said silicon nitride layer, to reduce the dimensions of the resulting mask in said photoresist or polymer layer by a desired amount, said lateral etching being substantially anisotropic and controllable as a function of time; and (f) etching said semiconductor substrate using the resulting mask in said photoresist or polymer layer.
Claim 18
Independent Claim
257 words
A method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, comprising: (a) depositing three layers on a semiconductor substrate, the bottom layer being of a photoresist or polymer material and in contact with the upper surface of said substrate, the intermediate layer being of silicon nitride and in contact with the upper surface of said bottom layer, and the upper layer being of a highly sensitive photoresist and in contact with the upper surface of said intermediate layer; (b) generating a desired mask pattern in said upper layer and transferring the pattern by RIE or plasma etching to said silicon nitride layer; (c) transferring the pattern to said photoresist or polymer layer by RIE, said silicon nitride layer serving as a mask, said photoresist or polymer layer being anisotropically etched with oxygen, using a gas flow of about 40 to about 60 sccm, a pressure of about 8 to about 12 μbar, and an energy density of about 0.2 to about 0.4 Watt/cm 2 , yielding angles of about 80° to about 85° in the mask in said photoresist or polymer layer; (d) removing said patterned silicon nitride layer by RIE or plasma etching; (e) laterally etching, after removal of said silicon nitride layer, to reduce the dimensions of the resulting mask in said photoresist or polymer layer by a desired amount, said lateral etching being substantially anisotropic and controllable as a function of time; and (f) etching said semiconductor substrate using the resulting mask in said photoresist or polymer layer.
Claim 19
Independent Claim
257 words
A method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, comprising: (a) depositing three layers on a semiconductor substrate, the bottom layer being of a photoresist or polymer material and in contact with the upper surface of said substrate, the intermediate layer being of silicon nitride and in contact with the upper surface of said bottom layer, and the upper layer being of a highly sensitive photoresist and in contact with the upper surface of said intermediate layer; (b) generating a desired mask pattern in said upper layer and transferring the pattern by RIE or plasma etching to said silicon nitride layer; (c) transferring the pattern to said photoresist or polymer layer by RIE, said silicon nitride layer serving as a mask, said photoresist or polymer layer being anisotropically etched with oxygen, using a gas flow of about 40 to about 60 sccm, a pressure of about 8 to about 12 μbar, and an energy density of about 0.2 to about 0.4 Watt/cm 2 , yielding angles of about 80° to about 85° in the mask in said photoresist or polymer layer; (d) removing said patterned silicon nitride layer by RIE or plasma etching; (e) laterally etching, after removal of said silicon nitride layer, to reduce the dimensions of the resulting mask in said photoresist or polymer layer by a desired amount, said lateral etching being substantially anisotropic and controllable as a function of time; and (f) etching said semiconductor substrate using the resulting mask in said photoresist or polymer layer.
Claim 20
Dependent Claim
58 words
The method of claim 16, wherein for increasing the positive angle, the mask in said photoresist or polymer layer is subjected to a facetting step in oxygen, using a gas flow of about 15 to about 25 sccm, a pressure of < about 1 μbar, and an energy density of about 0.2 to about 0.4 Watt/cm 2 .
Claim 21
Independent Claim
247 words
A method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, comprising: (a) depositing three layers on a semiconductor substrate, the bottom layer being of a photoresist or polymer material and in contact with the upper surface of said substrate, the intermediate layer being of silicon nitride and in contact with the upper surface of said bottom layer, and the upper layer being of a highly sensitive photoresist and in contact with the upper surface of said intermediate layer; (b) generating a desired mask pattern in said upper layer and transferring the pattern by RIE or plasma etching to said silicon nitride layer; (c) transferring the pattern to said photoresist or polymer layer by RIE, using oxygen, said silicon nitride layer serving as a mask; (d) removing said patterned silicon nitride layer by RIE or plasma etching; (e) laterally etching, after removal of said silicon nitride layer, to reduce the dimensions of the resulting mask in said photoresist or polymer layer by a desired amount, said lateral etching being substantially anisotropic and controllable as a function of time; and (f) etching a structure with angles < about 90° into said semiconductor substrate using the resulting mask in said photoresist or polymer layer, wherein said substrate comprises polysilicon and a mixture, in volume per cent, of about 6 to about 8% SF 6 , about 2 to about 3% Cl 2 , with the remainder helium is used to RIE etch said substrate.
Claim 22
Independent Claim
247 words
A method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, comprising: (a) depositing three layers on a semiconductor substrate, the bottom layer being of a photoresist or polymer material and in contact with the upper surface of said substrate, the intermediate layer being of silicon nitride and in contact with the upper surface of said bottom layer, and the upper layer being of a highly sensitive photoresist and in contact with the upper surface of said intermediate layer; (b) generating a desired mask pattern in said upper layer and transferring the pattern by RIE or plasma etching to said silicon nitride layer; (c) transferring the pattern to said photoresist or polymer layer by RIE, using oxygen, said silicon nitride layer serving as a mask; (d) removing said patterned silicon nitride layer by RIE or plasma etching; (e) laterally etching, after removal of said silicon nitride layer, to reduce the dimensions of the resulting mask in said photoresist or polymer layer by a desired amount, said lateral etching being substantially anisotropic and controllable as a function of time; and (f) etching a structure with angles < about 90° into said semiconductor substrate using the resulting mask in said photoresist or polymer layer, wherein said substrate comprises polysilicon and a mixture, in volume per cent, of about 6 to about 8% SF 6 , about 2 to about 3% Cl 2 , with the remainder helium is used to RIE etch said substrate.
References Cited (Backward Citations)
US3201239A
Cited
US3770433A
Cited
US4244799A
Cited
WO1980000639A1
Cited
US4209349A
Cited
US4234362A
Cited
US4209350A
Cited
US4256514A
Cited
US4397937A
Cited
EP0098318A1
Cited
US4589952A
Cited
US4502914A
Cited
EP0146789A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-24 | 1994-06-25 | 1994-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-24 | 1998-06-25 | 1998-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-24 | 2002-06-25 | 2002-12-25 | $7700.00 | Window Closed / Lapsed |