Error correction and detection apparatus and method

Claim 2

Apparatus for receiving input digital data coded using a predetermined error correction code, said apparatus comprising first means capable of correcting a first number of errors in the received data and capable of detecting errors in the received data at a first probability rate; second means capable of correcting a second number of errors in the received data, which is greater than said first number of errors, and capable of detecting errors in the received data at a second probability rate less than said first probability rate; means for deriving an error signal from said received data; and control means for applying said received data to said first means, and subsequently in response to said error signal indicating a first predetermined number of corrected errors in said received data, which is less than or equal to said first number, thereafter applying said received data to said second means, and thereafter in response to a subsequent error signal indicating a second predetermined number of corrected errors in said received data, which is less than or equal to said second number and greater than said first number, thereafter again applying said received data to said first means.

Claim 3

The apparatus of claim 1 wherein said first predetermined number is equal to zero.

Claim 4

The apparatus of claim 2 wherein said second predetermined number is equal to said second number.

Claim 5

The apparatus of claim 1 wherein said second predetermined error number is equal to said second number and said control means does not apply said received data to said first means when the number of corrected errors is less than said second number.

Claim 6

The apparatus of claim 1 further comprising means for interfacing the apparatus to a digital data link to receive an input signal.

Claim 7

A data communication system including a data transmitter and a data receiver connected over a data path, said data transmitter comprising means for generating and transmitting digital data coded using an error correcting code to said receiver; and said receiver comprising means for receiving said digital data; first means capable of correcting a first number of errors in the received data and capable of detecting errors in the received data at a first probability rate; second means capable of correcting a second number of errors in the received data, which is greater than said first number of errors, and capable of detecting errors in the received data at a second probability rate less than said first probability rate; means for deriving an error signal from said received data; and control means for applying said received data to said first means, and subsequently in response to said error signal indicating a first predetermined number of corrected errors in said received data, which is less than or equal to said first number, thereafter applying said received data to said second means, and thereafter in response to a subsequent error signal indicating a second predetermined number of corrected errors in said received data, which is less than or equal to said second number and greater than said first number, thereafter again applying said received data to said first means.

Claim 8

A data communication system including a data transmitter and a data receiver connected over a data path, said data transmitter comprising means for generating and transmitting digital data coded using an error correcting code to said receiver; and said receiver comprising means for receiving said digital data; first means capable of correcting a first number of errors in the received data and capable of detecting errors in the received data at a first probability rate; second means capable of correcting a second number of errors in the received data, which is greater than said first number of errors, and capable of detecting errors in the received data at a second probability rate less than said first probability rate; means for deriving an error signal from said received data; and control means for applying said received data to said first means, and subsequently in response to said error signal indicating a first predetermined number of corrected errors in said received data, which is less than or equal to said first number, thereafter applying said received data to said second means, and thereafter in response to a subsequent error signal indicating a second predetermined number of corrected errors in said received data, which is less than or equal to said second number and greater than said first number, thereafter again applying said received data to said first means.

Claim 11

Apparatus for receiving input digital data coded using an error correction code, said apparatus comprising error correcting circuit (ECC) means for detecting one or more errors and for correcting a single-bit error in the received data using said error correction code, error detecting circuit (EDC) means for detecting one or more errors in the received data using said error correction code, means for deriving an error signal in a predetermined manner from said received data, and switch means responsive to the absence of an error signal received from said deriving means for switching the detecting of said received data from said EDC means to said ECC means and responsive to the presence of said error signal for switching the detecting of said received data from said ECC means to said EDC means.

Claim 12

Apparatus for receiving input digital data coded using an error correction code, said apparatus comprising error correcting circuit (ECC) means for detecting one or more errors and for correcting a single-bit error in the received data using said error correction code, error detecting circuit (EDC) means for detecting one or more errors in the received data using said error correction code, means for deriving an error signal in a predetermined manner from said received data, and switch means responsive to the absence of an error signal received from said deriving means for switching the detecting of said received data from said EDC means to said ECC means and responsive to the presence of said error signal for switching the detecting of said received data from said ECC means to said EDC means.

Claim 13

The apparatus of claim 8 wherein said switch means does not switch from said EDC means to said ECC means in response to an error signal derived in said predetermined manner from said received data and does not switch from said ECC means to said EDC means in response to a no-error signal derived in said predetermined manner from said received data.

Claim 14

The apparatus of claim 8 wherein said EDC means includes a syndrome circuit for processing the received data utilizing the same process used to generate said error correction code and generating an error and a no-error signal in response to the received data.

Claim 15

The apparatus of claim 10 wherein said syndrome circuit includes means for processing groups of data bits from the received data.

Claim 16

The apparatus of claim 8 wherein said ECC means includes a syndrome circuit for processing the received data utilizing the same process used to generate said error correction code and for generating an error and a no-error signal, said error signal representing remainder term after said processing and said no-error signal representing no remainder term after said processing, remainder list and comparison means for comparing the remainder term with a list of predefined remainder terms to determine a bit position in the received data where an error exists, and means responsive to a signal indicating the bit position of an error in the received data for inverting the data in said bit position.

Claim 17

The apparatus of claim 12 wherein said switch means includes means for gating the received data for processing by a particular one of said EDC means and said ECC means depending on the existing state of said switch means and said remainder term.

Claim 18

The apparatus of claim 8 wherein said error correction code is generated using a CRC code.

Claim 19

The apparatus of claim 8 further comprising means for interfacing the apparatus to a digital data link to receive said input digital data.

Claim 20

The apparatus of claim 8 wherein said input data includes a header and information bits and wherein said error correction code is generated for said header bits and wherein said ECC means and EDC means perform their respective operations on said header bits.

Claim 21

A data communication system including a data transmitter and a data receiver connected over a data path, said data transmitter comprising means for generating a data message including an error correction code and means for transmitting said data message to said receiver, and said receiver comprising means for receiving said data message, an error correcting circuit (ECC) means for detecting one or more errors and correcting a single-bit error in the received data message using said error correction code, an error detecting circuit (EDC) means for detecting one or more errors in the received data message using said error correction code and means for deriving an error signal in a predetermined manner from said received data, and switch means responsive to the absence of an error signal received from said deriving means for switching the detecting of said received data from said EDC means to said ECC means and responsive to the presence of said error signal for switching the detecting of said received data message from said ECC means to said EDC means.

Claim 22

A data communication system including a data transmitter and a data receiver connected over a data path, said data transmitter comprising means for generating a data message including an error correction code and means for transmitting said data message to said receiver, and said receiver comprising means for receiving said data message, an error correcting circuit (ECC) means for detecting one or more errors and correcting a single-bit error in the received data message using said error correction code, an error detecting circuit (EDC) means for detecting one or more errors in the received data message using said error correction code and means for deriving an error signal in a predetermined manner from said received data, and switch means responsive to the absence of an error signal received from said deriving means for switching the detecting of said received data from said EDC means to said ECC means and responsive to the presence of said error signal for switching the detecting of said received data message from said ECC means to said EDC means.