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US4979009A
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Heterojunction bipolar transistor
Assignee: Hitachi Ltd
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Filing: 1989-09-29
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Granted: 1990-12-18
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Expires: 2009-09-29
Abstract
Abstract 2A heterojunction bipolar transistor is disclosed in which a region of a base layer which extends in the vicinity of the interface between the base layer and an emitter layer is doped with an impurity at a higher concentration than that in the inside of the base layer to thereby form a built-in field by which carriers injected from the emitter are caused to drift to the inside of the base layer. In the transistor having this structure, the current gain does not depend on the emitter area, and it is possible to obtain a large current gain with a small emitter area.
Inventors
- 👤 Chushiro Kusano
- 👤 Tomonori Tanoue
- 👤 Katsuhiko Mitani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:18
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/80; H10D10/821
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
51 words
A heterojunction bipolar transistor wherein a base layer of said transistor includes a thin portion in contact with an emitter layer of said transistor said thin portion having a higher impurity concentration than an intermediate portion of said base layer, and wherein said base layer does not contain a heterojunction therein.
Claim 2
Dependent Claim
51 words
A heterojunction bipolar transistor wherein a base layer of said transistor includes a thin portion in contact with an emitter layer of said transistor said thin portion having a higher impurity concentration than an intermediate portion of said base layer, and wherein said base layer does not contain a heterojunction therein.
Claim 3
Dependent Claim
44 words
A heterojunction bipolar transistor according to claim 1, wherein said base layer further includes a second thin portion in contact with a collector layer of said transistor, said second thin portion having a higher impurity concentration than said intermediate portion of said base layer.
Claim 4
Dependent Claim
96 words
A heterojunction bipolar transistor comprising: a substrate; a collector layer formed on said substrate; a base layer formed on said collector layer, wherein said base layer does not contain a heterojunction therein; an emitter layer formed on said base layer; and electrodes for contacting said emitter layer and said base layer; wherein said base layer includes a first thin region in contact with said collector layer, and a second thin region in contact with said emitter layer, said first and second thin regions having a higher impurity concentration than an intermediate region of said base layer.
Claim 5
Dependent Claim
96 words
A heterojunction bipolar transistor comprising: a substrate; a collector layer formed on said substrate; a base layer formed on said collector layer, wherein said base layer does not contain a heterojunction therein; an emitter layer formed on said base layer; and electrodes for contacting said emitter layer and said base layer; wherein said base layer includes a first thin region in contact with said collector layer, and a second thin region in contact with said emitter layer, said first and second thin regions having a higher impurity concentration than an intermediate region of said base layer.
Claim 6
Dependent Claim
51 words
A heterojunction bipolar transistor according to claim 3, wherein said collector layer includes a first region in contact with said substrate, and a second region in contact with said base layer, said first region of said collector layer having a higher impurity concentration than said second region of said collector layer.
Claim 7
Dependent Claim
19 words
A heterojunction bipolar transistor according to claim 3, further including an ohmic contact layer formed on said emitter layer.
Claim 8
Dependent Claim
19 words
A heterojunction bipolar transistor according to claim 3, wherein said heterojunction bipolar transistor is an NPN heterojunction bipolar transistor.
Claim 9
Dependent Claim
19 words
A heterojunction bipolar transistor according to claim 3, wherein said heterojunction bipolar transistor is a PNP heterojunction bipolar transistor.
References Cited (Backward Citations)
JPS59106154A
Cited
EP0132025A2
Cited
JPS60242671A
Cited
JPS6122936A
Cited
JPS6233462A
Cited
US4811070A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-17 | 1994-06-18 | 1994-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-17 | 1998-06-18 | 1998-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-17 | 2002-06-18 | 2002-12-18 | $7700.00 | Window Closed / Lapsed |