US4977335A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low driving voltage operation logic circuit
Assignee: Toshiba Corp
•
Filing: 1989-07-05
•
Granted: 1990-12-11
•
Expires: 2009-07-05
Abstract
Abstract A low driving voltage operation logic circuit responsive to a power source voltage applied between a pair of power source terminals for modifying an input signal according to a predetermined logic pattern. The logic circuit includes an input control circuit having a plurality of input transistors for generating a pair of control signals, each having a level opposite to the other, in response to the input signal and a differential circuit having a plurality of paired transistors for dividing the frequency of the control signals, the input transistors each having an emitter area substantially larger than the emitter area of each paired transistor and the logic circuit including only a single base to emitter junction corresponding to each input transistor between the power source terminals.
Inventors
- 👤 Atsusi Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 04:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; H03K3/289
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
120 words
A low driving voltage operation logic circuit responsive to a power source voltage applied between a pair of power source terminals for modifying an input signal according to a predetermined logic pattern, comprising: input control means including a plurality of input transistors, for generating a pair of control signals, each having a level opposite to the other, in response to the input signal; and differential means including a plurality of paired transistors for dividing the frequency of the control signals, the input transistors each having an emitter area substantially larger than the emitter area of each paired transistor, and the logic circuit including only a single base to emitter junction corresponding to each input transistor between the power source terminals.
Claim 2
Dependent Claim
120 words
A low driving voltage operation logic circuit responsive to a power source voltage applied between a pair of power source terminals for modifying an input signal according to a predetermined logic pattern, comprising: input control means including a plurality of input transistors, for generating a pair of control signals, each having a level opposite to the other, in response to the input signal; and differential means including a plurality of paired transistors for dividing the frequency of the control signals, the input transistors each having an emitter area substantially larger than the emitter area of each paired transistor, and the logic circuit including only a single base to emitter junction corresponding to each input transistor between the power source terminals.
Claim 3
Dependent Claim
39 words
The logic circuit of claim 1 also including power reducing means connected between one of the power source terminals and the differential means for supplying an operating voltage lower than the power source voltage to the input control means.
Claim 4
Dependent Claim
15 words
The logic circuit of claim 1 wherein the differential means comprises a D-type flip-flop circuit.
Claim 5
Dependent Claim
16 words
The logic circuit of claim 1 wherein the differential means includes a master-slave type flip-flop circuit.
Claim 6
Dependent Claim
39 words
The logic circuit of claim 1 wherein each input transistor corresponds to a pair of the paired transistors, and the respective ratios of the emitter areas of each input transistor of the corresponding pair of paired transistors are unequal.
Claim 7
Dependent Claim
23 words
The logic circuit of claim 1 wherein each of the differential means and the input control means includes at least one current source.
References Cited (Backward Citations)
US3728560A
Cited
US3728561A
Cited
US4276488A
Cited
US4349753A
Cited
US4357547A
Cited
US4528465A
Cited
US4578599A
Cited
JPS61177811A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-10 | 1994-06-11 | 1994-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-10 | 1998-06-11 | 1998-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-10 | 2002-06-11 | 2002-12-11 | $7700.00 | Window Closed / Lapsed |