CMOS waveform digitizer

Abstract

Abstract An integrated circuit for digitizing a dynamic waveform with a resolution that is much higher than that which is achievable under prior art methods is disclosed. A reference clock signal T r is provided as input to at least two L-type registers over a synchronous delay line (SDL). The reference clock signal is also coupled to the L ports of the L-type registers over a sample enable circuit. The incoming waveform is input in parallel to both L-type registers. The SDL generates timing pulses at intervals that are separated by T r /N, where N is the number of taps in the SDL. N corresponds to the equally spaced intervals at which the incoming waveform is sampled. The L-type register samples the incoming waveform according to control signals provided by the sample enable circuit. The control signals are required to guarantee the set-up and hold times for the flip-flops in the L-type register. Thus, the resolution of the digitized waveform is T r /N. This resolution is N times better than that achievable with the prior art method. The dual arrangement of the L-type register also forecloses the occurrence of any metastable states in the flip-flops of the L-type register, thus guaranteeing a continuous sampling of the incoming waveform. The outputs from the dual L-type registers are input to a muliplexer and further to a D-type register before it is outputted as a digitized waveform. The muliplexer selects the appropriate stream of sampled waveform alternatively from one of the L-type registers. Therefore, the present inventions also provide precise information about the transitions of the dynamic waveform by digitizing of the incoming waveform continuously.

Inventors

• 👤 Mel Bazes

Bibliographic Details