Apparatus for converting analog signals into digital signals and digital signals into analog signals

Claim 1

In a telecommunication system having subscriber stations constructed to send and receive analog signals and wherein signals are transmitted from subscriber station to subscriber station in digital form, apparatus for converting an incoming digital signal into an analog signal and an analog signal into an outgoing digital signal comprising: input register means for receiving incoming digital signals; buffer register means having a plurality of bistable stages having first inputs connected to said input register means for receiving the incoming digital signals; digital to analog converter means having inputs connected to outputs of said bistable stages of said buffer register for converting the incoming digital signals to analog signals; analog output means connected to receive the output of said digital to analog converter; comparator means having one input connected to receive the output of said digital to analog converter and another input connected to receive an analog signal to be converted, the output of said comparator means being coupled to second inputs of said bistable stages of said buffer register; output register means having inputs coupled to the outputs of said bistable stages of said buffer register for receiving the outgoing digital signals corresponding to the analog signal received by said another input of said comparator means; multistage binary counter means having a predetermined starting position and a plurality of outputs coupled to said buffer register means for enabling said buffer register and said digital to analog converter to convert the incoming digital signals to analog signals during a first portion of the counting interval and for enabling the combination of said analog comparator, said buffer register and said analog to digital converter to convert analog signals to outgoing digital signals during a second portion of the counting interval; clock generator means connected to said binary counter means for driving said binary counter means; and initiating means for actuating said binary counter means responsive to the reception of a predetermined calling bit sequence in said input register means, said initiating means including detector means connected to said input register means for producing a first signal responsive to the appearance of the calling bit sequence in said input register, sensing means for producing a second signal responsive to the subscriber station being rendered operative and first switching means for connecting said clock generator to said binary counter means when said first and second signals appear in coincidence.