Abstract The specification discloses circuitry for compensating integrated circuits for negative internal ground voltage glitches. An output transistor (30) receives input signals at its base and has an emitter connected through a Schottky diode (32) to internal circuit ground. The compensation circuit includes a transistor (42) coupled to the base of transistor (30) and having an emitter also coupled to internal circuit ground. A capacitor (44) is connected between the base of transistor (42) and a source of bias voltage. Transistor (42) is rendered conductive by the occurrence of negative voltage glitches on the circuit ground, thus reducing voltage on the base of transistor (30) to prevent premature conduction by transistor (30).
An integrated circuit including compensation circuitry, comprising: a plurality of devices on a semiconductor layer, said device interconnected; first and second reference nodes within said plurality and connected to first and second external references, respectively; and a switch connected between an input of one of said devices and said first reference node, said switch activated by transient increases in the difference of potential between said first and second reference nodes of magnitude that would activate said one device if said device were otherwise inactive in accordance with the potential on said input.
Claim 2
Dependent Claim
92 words
An integrated circuit including compensation circuitry, comprising: a plurality of devices on a semiconductor layer, said device interconnected; first and second reference nodes within said plurality and connected to first and second external references, respectively; and a switch connected between an input of one of said devices and said first reference node, said switch activated by transient increases in the difference of potential between said first and second reference nodes of magnitude that would activate said one device if said device were otherwise inactive in accordance with the potential on said input.
Claim 3
Dependent Claim
52 words
The integrated circuit of claim 1, wherein: said first reference node is an internal ground; said second reference node is a supply voltage node; said switch includes an NPN bipolar transistor with emitter connected to said internal ground, collector connected to said input, and base capacitively coupled to said supply voltage node.