Method for making an electrically erasable programmable read only memory cell having a three dimensional floating gate

Claim 1

A method of forming an electrically programmable read only memory cell on a semiconductor substrate, comprising: forming a moat region of a first conductivity type in said substrate; etching a trench through said moat region; doping the bottom edge and walls of said trench to create a region of said first conductivity type extending continuously to said moat region; conformally depositing a pair of conducting layers over said trench and a portion of said substrate insulated from said substrate by a selected thickness of insulator material and from each other; wherein said conducting layers form a floating gate and a control gate for said memory cell.

Claim 2

A method of forming an electrically programmable read only memory cell on a semiconductor substrate, comprising: forming a moat region of a first conductivity type in said substrate; etching a trench through said moat region; doping the bottom edge and walls of said trench to create a region of said first conductivity type extending continuously to said moat region; conformally depositing a pair of conducting layers over said trench and a portion of said substrate insulated from said substrate by a selected thickness of insulator material and from each other; wherein said conducting layers form a floating gate and a control gate for said memory cell.

Claim 5

A method for forming a floating gate memory cell, comprising: forming a moat region of first conductivity type in a substrate of second conductivity type; etching a trench through said moat region, said trench having walls and a bottom edge; doping said walls and said bottom edge of said trench such that regions of said first conductivity type extend continuously to said moat region; forming an insulating layer over said trench walls, said trench bottom edge, said moat region and said substrate; forming a first conductive layer over said insulating layer; and forming a second conductive layer over said first conductive layer, said second conductive layer insulated from said first conductive layer and insulated from said trench walls, said trench bottom edge, said moat region and said substrate; wherein said first conductive layer forms said floating gate of said memory cell and wherein said second conductive layer forms a control gate of said memory cell.

Claim 6

A method for forming a floating gate memory cell, comprising: forming a moat region of first conductivity type in a substrate of second conductivity type; etching a trench through said moat region, said trench having walls and a bottom edge; doping said walls and said bottom edge of said trench such that regions of said first conductivity type extend continuously to said moat region; forming an insulating layer over said trench walls, said trench bottom edge, said moat region and said substrate; forming a first conductive layer over said insulating layer; and forming a second conductive layer over said first conductive layer, said second conductive layer insulated from said first conductive layer and insulated from said trench walls, said trench bottom edge, said moat region and said substrate; wherein said first conductive layer forms said floating gate of said memory cell and wherein said second conductive layer forms a control gate of said memory cell.