Patent US4974241A successfully refreshed from Google Patents.
US4974241A
Expired / Lapsed
US
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Counter employing exclusive NOR gate and latches in combination
Assignee: STMicroelectronics lnc USA
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Filing: 1989-03-31
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Granted: 1990-11-27
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Expires: 2009-03-31
Abstract
Abstract The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.
Inventors
- 👤 David C. McClure
- 👤 Mark A. Lysinger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:27
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
293 words
An N bit counter comprising: (a) an N plurality of T flip flops, each of said T flip flops having a T input terminal, a clock input terminal, and first and second output terminals and further comprising: (i) an exclusive NOR gate, one input of which is connected to said T input terminal, a second input of which is coupled to said first output terminal; (ii) first transfer circuitry which couples the output of said exclusive NOR to an internal node when said clock signal is at a first logic state and which isolates the output of said exclusive NOR gate from said internal node when said clock signal is at a second logic state; (iii) second transfer circuitry which couples said internal node to said first output terminal when said clock signal is at said second logic state and which isolates said internal node from said first output terminal when said clock signal is at said first logic state; (iv) third transfer circuitry which couples said first output terminal ti said second output terminal when said clock signal is at said first logic state and which isolates said first output terminal from said second output terminal when said clock signal is at said second logic state; and (b) interconnection means for coupling together said N plurality of T flip flops such that the first and second outputs of said T flip flops toggle in a predetermined sequence in synchronization with a clock signal applied to said clock input terminal, said first output terminals of said T flip flops changing state in synchronization with the leading edge of said clock signal and said second output terminals of said T flip flops changing state in synchronization with the trailing edge of said clock signal.
Claim 2
Dependent Claim
293 words
An N bit counter comprising: (a) an N plurality of T flip flops, each of said T flip flops having a T input terminal, a clock input terminal, and first and second output terminals and further comprising: (i) an exclusive NOR gate, one input of which is connected to said T input terminal, a second input of which is coupled to said first output terminal; (ii) first transfer circuitry which couples the output of said exclusive NOR to an internal node when said clock signal is at a first logic state and which isolates the output of said exclusive NOR gate from said internal node when said clock signal is at a second logic state; (iii) second transfer circuitry which couples said internal node to said first output terminal when said clock signal is at said second logic state and which isolates said internal node from said first output terminal when said clock signal is at said first logic state; (iv) third transfer circuitry which couples said first output terminal ti said second output terminal when said clock signal is at said first logic state and which isolates said first output terminal from said second output terminal when said clock signal is at said second logic state; and (b) interconnection means for coupling together said N plurality of T flip flops such that the first and second outputs of said T flip flops toggle in a predetermined sequence in synchronization with a clock signal applied to said clock input terminal, said first output terminals of said T flip flops changing state in synchronization with the leading edge of said clock signal and said second output terminals of said T flip flops changing state in synchronization with the trailing edge of said clock signal.
Claim 3
Dependent Claim
188 words
A T flip flop having a T input, a clock input, and first and second outputs, comprising: an exclusive NOR gate having an input connected to the T input and an input connected to the first output; a first latch; a first gate connected to the clock input, to an output of said exclusive NOR gate, and an input of said first latch, wherein the exclusive NOR gate output is connected to the first latch input through said first gate only when the clock input has a first state; a second latch having an output connected to the first output; a second gate connected to an output of said first latch and to an input of said second latch, wherein the first latch output is connected to the second latch input only when the clock input has a second state; a third latch having an output connected to the second output; and a third gate connected to the first output and to an input of said third latch, wherein the first output is connected to the third latch input only when the clock input has the first state.
Claim 4
Dependent Claim
188 words
A T flip flop having a T input, a clock input, and first and second outputs, comprising: an exclusive NOR gate having an input connected to the T input and an input connected to the first output; a first latch; a first gate connected to the clock input, to an output of said exclusive NOR gate, and an input of said first latch, wherein the exclusive NOR gate output is connected to the first latch input through said first gate only when the clock input has a first state; a second latch having an output connected to the first output; a second gate connected to an output of said first latch and to an input of said second latch, wherein the first latch output is connected to the second latch input only when the clock input has a second state; a third latch having an output connected to the second output; and a third gate connected to the first output and to an input of said third latch, wherein the first output is connected to the third latch input only when the clock input has the first state.
Claim 5
Dependent Claim
69 words
The flip flop of claim 2, wherein each of said latches comprises: a first inverter having an input connected to the latch input and an output connected to the latch output; and a second inverter having an input connected to the latch output and an output connected to the latch input; wherein said third latch further includes a third inverter connected between the latch output and the second output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-26 | 1994-05-28 | 1994-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-26 | 1998-05-28 | 1998-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-26 | 2002-05-28 | 2002-11-27 | $7700.00 | Window Closed / Lapsed |