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US4972106A Expired / Lapsed US ⏱️ 0.0 years remaining

Binary-to-ternary converter for combining two binary signals

Assignee: AT&T Network Systems International BV
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Filing: 1989-03-17
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Granted: 1990-11-20
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Expires: 2009-03-17
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Abstract

Abstract A binary-to-ternary converter arrangement which achieves protective resistance against high outside voltages without having to compromise the voltage level of the positive and negative output ternary pulses. In so achieving, the minimum amplitude requirement of a CCITT recommendation of an output pulse for a given supply voltage is satisfied. This converter arrangement includes a parallel circuit of first and second series circuits. The first series circuit forms a main current path of two transistors and the second series circuit forms a current path of a diode, two resistors, and a third transistor. The different elements of these two circuits, along with a capacitor element, are interconnected in such a way as to eliminate the need for the use of a transformer altogether. The control electrodes of the first and second transistors serve as input ports and the junction port of the two resistors serves as the output port.

Inventors

  • 👤 Jan B. F. W. Ruijs

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 08:22
CPC Classifications
H; H03; H03M; H03M5/00; H03M5/02; H03M5/16; H03M5/18; H04; H04L; H04L5/00; H04L5/22

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 178 words
A binary-to-ternary converter for combining two binary signals into one ternary signal, characterized in that the binary-to-ternary converter comprises a parallel circuit of a first and a second series circuit, this parallel circuit comprising two supply terminals for connecting a supply voltage to said first and said second series circuits, said first series circuit being formed by the main current path of a first and a second transistor, respectively, said second series circuit being formed by a first diode, a first and a second resistor and the main current path of a third resistor, respectively, in the parallel circuit the junction of the first diode and the first resistor being connected via a first capacitor to the junction of the first and the second transistors, in the parallel circuit the control electrodes of the second and the third transistors being interconnected, in that the control electrodes of the first and the second transistors form the input ports to the binary-to-ternary converter, and in that the junction of the two resistors forms the output port of the binary-to-ternary converter.
Claim 2
Dependent Claim 178 words
A binary-to-ternary converter for combining two binary signals into one ternary signal, characterized in that the binary-to-ternary converter comprises a parallel circuit of a first and a second series circuit, this parallel circuit comprising two supply terminals for connecting a supply voltage to said first and said second series circuits, said first series circuit being formed by the main current path of a first and a second transistor, respectively, said second series circuit being formed by a first diode, a first and a second resistor and the main current path of a third resistor, respectively, in the parallel circuit the junction of the first diode and the first resistor being connected via a first capacitor to the junction of the first and the second transistors, in the parallel circuit the control electrodes of the second and the third transistors being interconnected, in that the control electrodes of the first and the second transistors form the input ports to the binary-to-ternary converter, and in that the junction of the two resistors forms the output port of the binary-to-ternary converter.
Claim 3
Dependent Claim 60 words
A binary-to-ternary converter as claimed in claim 1, characterized in that the control electrode of the first transistor is connected to the junction of the first diode and the first resistor via a third resistor, which control electrode forms one of said input ports to the binary-to-ternary converter via a parallel circuit of a second diode and a second capacitor.

References Cited (Backward Citations)

US3217316A Cited
US3337862A Cited
US3492496A Cited
US3660678A Cited
US4345164A Cited
JPS61292415A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-11-19 1994-05-21 1994-11-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-11-19 1998-05-21 1998-11-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-11-19 2002-05-21 2002-11-20 $7700.00 Window Closed / Lapsed

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