Resettable latch circuit

Claim 1

A reset circuit incorporated into a latch circuit, said latch circuit being of the type which receives a first input data signal and generates a first output signal at a first output terminal, after latching, in response to said first input data signal, said reset circuit operating to set said first output signal at a predetermined high or low state upon application of a first reset signal to said reset circuit, said reset circuit comprising: a first two terminal nonlinear device with a first terminal coupled to receive said first reset signal and a second terminal coupled to said first output terminal of said latch circuit, whereby, upon application of said first reset signal to said first terminal of said first nonlinear device, said first output terminal will assume the state of said first reset signal prior to said latch circuit latching, wherein said latch circuit generates a second output signal of a state opposite to that of said first output signal for application to a second output terminal, and wherein a second reset signal of opposite state as said first reset signal is applied to a first terminal of a second two terminal nonlinear device wherein a second terminal is coupled to said second output terminal, so that upon application of said second reset signal to said first terminal of said second nonlinear device, said second output terminal will assume the state of said second reset signal, wherein said latch circuit incorporates a hold circuit comprising a first differential transistor pair being enabled by an enable signal, said first differential transistor pair comprising a first transistor and a second transistor, said first transistor having a control terminal coupled to said second output terminal and a second terminal coupled to said first output terminal, said second transistor having a control terminal coupled to said first output terminal and a second terminal coupled to said second output terminal, said first transistor and said second transistor having third terminals being coupled together and connected to an enable circuit, said enable circuit, upon application of a first state of said enable signal to said enable circuit, causing a current to be drawn through said first differential pair, and wherein said second reset signal, through said second nonlinear device, and said second terminal of said second transistor are coupled to said second output terminal via a first level shifting means so that when said second terminal of said second transistor is at a high level, said level shifting means will apply a high signal to said second output terminal, and when said second reset signal is at a low level a low signal will be applied to said second output terminal.