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US3813558A Expired / Lapsed US ⏱️ 0.0 years remaining

Directional, non-volatile bistable resistor logic circuits

Assignee: International Business Machines Corp
•
Filing: 1972-06-26
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Granted: 1974-05-28
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Expires: 1992-06-26
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Abstract

Abstract A circuit consisting of a pair of bistable resistors connected in series at a node to which current may be applied and from which current may be drawn and having a source of potential connected to each bistable resistor is disclosed. The bistable resistors are oriented physically in the same direction such that current in a given direction which exceeds a threshold and which switches the bistable resistors into a high resistance state can be characterized as the forward direction. Conversely, current in the opposite direction to the given direction which, when it exceeds a threshold, switches the devices from a high resistance state into a low resistance state can be characterized as the backward direction. With appropriately applied potentials to each of the bistable resistors, with one potential more positive than the other, current can be made to flow in the forward and backward directions. In the forward direction, both resistors are switched into or remain in a high resistance or RH state. When current flows in the backward direction through the pair of bistable resistors, they switch into or remain in the low resistance or RL state. By applying the same potentials to the bistable resistors and causing current to flow into or out of the node at which the bistable resistors are connected, it is possible to cause the pair of resistors to assume a low resistance high resistance state and, a high resistance low resistance state, respectively. Thus, by simply controlling the potentials and the direction of current flow through each of the pair of bistable resistors, four, non-volatile, stable states are achievable as opposed to a maximum of two volatile states in similarly arranged tunnel diode circuits, for example. Because the arrangements shown are inexpensive, easy to fabricate and permit high packing densities, circuits such as shift registers which utilize large numbers of similarly arranged logic circuits are most attractive. In addition, the nanosecond switching speeds available in bistable resistors make them superior to other known switching devices of slower switching speed. A shift register circuit incorporating three of the four non-volatile, stable states available with the logic circuits is also disclosed. The shift register utilizes a low resistance-high resistance state to represent a binary ''''one'''' and a high resistance-high resistance state and a high resistance-low resistance state to represent a binary ''''zero.

Inventors

  • 👤 P Krick
  • 👤 P Pleshko

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 19:33
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; G; G11; G11C; G11C19/00; G11C19/28

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 253 words
A shift register circuit comprising at least first and second shift register stages each of said shift register stages including at least first and second bistable resistors connected in series at a node said bistable resistors having a characteristic such that current in one direction in excess of a threshold causes said resistor to switch to a high resistance state and such that current in a direction opposite to said one direction in excess of a threshold causes said resistor to switch into a low resistance state, means connected to said first and second shift register stages for setting said first and second bistable resistors thereof in a high resistance-low resistance state, respectively, during respective first and second reset intervals, means connected to said first shift register stage for applying signals representative of binary information to cause said first and second bistable resistors to assume one of the states, low resistance-high resistance respectively, and remaining in the state assumed during said first reset interval, means connected during a transfer interval to said first and second bistable resistors of said first and second stages for transferrring a signal representative of a binary ''''1'''' and a binary ''''0'''' from said first stage to said second stage causing said first and second resistors of said second stage to assume one of the states, low resistance-high resistance, respectively, and remaining in the state assumed during said second reset interval, and another bistable resistor connected in parallel with said first bistable resistor of said first and second stages.
Claim 2
Dependent Claim 253 words
A shift register circuit comprising at least first and second shift register stages each of said shift register stages including at least first and second bistable resistors connected in series at a node said bistable resistors having a characteristic such that current in one direction in excess of a threshold causes said resistor to switch to a high resistance state and such that current in a direction opposite to said one direction in excess of a threshold causes said resistor to switch into a low resistance state, means connected to said first and second shift register stages for setting said first and second bistable resistors thereof in a high resistance-low resistance state, respectively, during respective first and second reset intervals, means connected to said first shift register stage for applying signals representative of binary information to cause said first and second bistable resistors to assume one of the states, low resistance-high resistance respectively, and remaining in the state assumed during said first reset interval, means connected during a transfer interval to said first and second bistable resistors of said first and second stages for transferrring a signal representative of a binary ''''1'''' and a binary ''''0'''' from said first stage to said second stage causing said first and second resistors of said second stage to assume one of the states, low resistance-high resistance, respectively, and remaining in the state assumed during said second reset interval, and another bistable resistor connected in parallel with said first bistable resistor of said first and second stages.
Claim 3
Dependent Claim 35 words
A shift register stage in accordance with claim 1 further including means connected to said first and second bistable resistors of said second stage for applying a signal representative of binary information to an output.
Claim 4
Dependent Claim 50 words
A shift register stage in accordance with claim 2 wherein said means connected to said first and second bistable resistors of said second stage includes a pulsed voltage source at positive potential connected to said first resistor and a pulsed voltage source at reference potential connected to said second resistor.
Claim 5
Dependent Claim 57 words
A shift register stage according to claim 1 wherein said means for setting said first and second bistable resistors in a high resistance-low resistance state, respectively, includes first and second pulsed sources connected to said first and second resistors held at positive potential and another pulsed source held at ground potential connected to said node via diodes.
Claim 6
Dependent Claim 18 words
A shift register stage according to claim 4 further including a resistance connected in parallel with said diodes.
Claim 7
Dependent Claim 48 words
A shift register stage according to claim 1 wherein said means for applying signals includes a pulsed current source adapted to apply one of current and no current to said node of said first stage during a clocked transfer interval via a diode and a current limiting resistor.
Claim 8
Dependent Claim 106 words
A shift register stage according to claim 1 wherein said means connected to said first and second bistable resistors of said first and second stages for transferring a signal from said first stage to said second stage includes first and second pulsed voltage sources connected to said first and second stages said first voltage source connected to said first stage being at a positive potential and said second voltage source connected to said first stage and said first and second voltage sources connected to said second stage being at reference potential during said transfer interval said nodes being connected via a diode and current limiting resistor.
Claim 9
Dependent Claim 22 words
A shift register according to claim 1 wherein said first and second bistable resistors having the same high and low resistance values.
Claim 10
Dependent Claim 23 words
A shift register according to claim 1 wherein said first bistable resistor has a lower high resistance value than said second bistable resistor.
Claim 11
Dependent Claim 26 words
A shift register in accordance with claim 1 wherein said first and second and said another bistable resistor have the same high and low resistance values.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-05-27 1977-11-26 1978-05-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-05-27 1981-11-26 1982-05-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-05-27 1985-11-26 1986-05-28 $7700.00 Window Closed / Lapsed

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