US4965872A
Expired / Lapsed
US
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MOS-enhanced, self-aligned lateral bipolar transistor made of a semiconductor on an insulator
Assignee: Raytheon Co
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Filing: 1988-09-26
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Granted: 1990-10-23
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Expires: 2008-09-26
Abstract
Abstract A self-aligned, lateral bipolar transistor is disclosed having at least one insulated metal gate for control of the base. The device has a Semiconductor-On-Insulator structure that reduces parasitic capacitances. Proper gate control provides a high and controllable gain of the device and also turns off the parasitic transistors. The device achieves variable, high gains as well as high frequencies due to the use of the gate. It requires no masking or doping manufacturing steps in addition to those used in making standard CMOS circuits, and is CMOS compatible. In a preferred embodiment, a second insulated metal back gate is used to further enhance the operation of the device.
Inventors
- 👤 Prahalad K. Vasudev
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:33
CPC Classifications
H; H10; H10D; H10D88/00; H10D10/00; H10D10/311; H10D12/00; H10D84/00; H10D84/101; H10D84/121
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
184 words
An improved, lateral bipolar transistor, comprising: a first insulation layer; a first semiconductor layer adjacent to said first insulation layer, said first semiconductor layer having emitter, base, and collector regions formed therein in a lateral bipolar transistor configuration; a first gate on said first insulation layer aligned with said base region and separated from said base region by said first insulation layer, said first gate controlling the base resistance in response to voltage signals applied to said first gate; means for establishing electrical conditions to said emitter, base, and collector regions and an active electrical connection to said first gate; a second insulation layer on the opposite side of said first semiconductor layer from said first insulation layer; a second gate on said second insulation layer separated from the base region by said second insulation layer, said second gate controlling the base resistance independent of said first gate in response to voltage signals applied to said second gate, the interface between said second insulation layer and aid second gate being substantially planar; and means for establishing an active electrical connection to said second gate.
Claim 2
Dependent Claim
184 words
An improved, lateral bipolar transistor, comprising: a first insulation layer; a first semiconductor layer adjacent to said first insulation layer, said first semiconductor layer having emitter, base, and collector regions formed therein in a lateral bipolar transistor configuration; a first gate on said first insulation layer aligned with said base region and separated from said base region by said first insulation layer, said first gate controlling the base resistance in response to voltage signals applied to said first gate; means for establishing electrical conditions to said emitter, base, and collector regions and an active electrical connection to said first gate; a second insulation layer on the opposite side of said first semiconductor layer from said first insulation layer; a second gate on said second insulation layer separated from the base region by said second insulation layer, said second gate controlling the base resistance independent of said first gate in response to voltage signals applied to said second gate, the interface between said second insulation layer and aid second gate being substantially planar; and means for establishing an active electrical connection to said second gate.
Claim 3
Dependent Claim
21 words
The bipolar transistor of claim 1, further comprising: a second semiconductor layer between said first gate and said first insulation layer.
Claim 4
Dependent Claim
23 words
The bipolar transistor of claim 1, wherein said first semiconductor layer is made of a material having a low density of crystalline defects.
Claim 5
Dependent Claim
18 words
The bipolar transistor of claim 1, wherein said first gate is self-aligned with respect to said base region.
Claim 6
Dependent Claim
17 words
The bipolar transistor of claim 1, wherein the width of said base region is about 0.5-1.0 micron.
Claim 7
Dependent Claim
18 words
The bipolar transistor of claim 1, wherein the height of said first semiconductor layer is about 0.5 microns.
Claim 8
Dependent Claim
21 words
The bipolar transistor of claim 1, further comprising: an overlaid insulative layer surrounding said first semiconductor layer and protecting said transistor.
Claim 9
Dependent Claim
188 words
A lateral bipolar transistor having a variable common emitter current gain, comprising: a first insulation layer; a first semiconductor layer adjacent to said first insulation layer, aid first semiconductor layer having emitter, base, and collector regions formed therein in a lateral bipolar transistor configuration; a first gate on said first insulation layer aligned with said base region an separated from said base region by said first insulation layer, aid first gate controlling the common emitter current gain of said transistor in response to voltage signals applied to said first gate; means for establishing electrical connections to said emitter, base, and collector regions and an active electrical connection to said first gate; a second insulation layer on the opposite side of said first semiconductor layer from said first insulation layer; a second gate on said second insulation layer for controlling the common emitter current gain of said transistor independent of said first gate in response to voltage signals applied to said second gate, the interface between said second insulation layer and said second gate being substantially planar; and means for establishing an active electrical connection to said second gate.
Claim 10
Dependent Claim
188 words
A lateral bipolar transistor having a variable common emitter current gain, comprising: a first insulation layer; a first semiconductor layer adjacent to said first insulation layer, aid first semiconductor layer having emitter, base, and collector regions formed therein in a lateral bipolar transistor configuration; a first gate on said first insulation layer aligned with said base region an separated from said base region by said first insulation layer, aid first gate controlling the common emitter current gain of said transistor in response to voltage signals applied to said first gate; means for establishing electrical connections to said emitter, base, and collector regions and an active electrical connection to said first gate; a second insulation layer on the opposite side of said first semiconductor layer from said first insulation layer; a second gate on said second insulation layer for controlling the common emitter current gain of said transistor independent of said first gate in response to voltage signals applied to said second gate, the interface between said second insulation layer and said second gate being substantially planar; and means for establishing an active electrical connection to said second gate.
Claim 11
Dependent Claim
22 words
The lateral bipolar transistor of claim 8, further comprising: a second semiconductor layer between said first gate and said first insulation layer.
Claim 12
Dependent Claim
31 words
The bipolar transistor of claim 8, said second gate comprising a doped semiconductor layer in contact with said second insulation layer, and a conductive contact layer on said doped semiconductor layer.
Claim 13
Dependent Claim
21 words
The bipolar transistor of claim 10, wherein the interface between said doped semiconductor layer and said contact layer is substantially planar.
Claim 14
Dependent Claim
209 words
An improved, lateral bipolar transistor, comprising: a first insulation layer; a first semiconductor layer adjacent to said first insulation layer, said first semiconductor layer having emitter, base, and collector regions formed therein in a lateral bipolar transistor configuration; a first gate on said first insulation layer aligned with said base region and separated from said base region by said first insulation layer, said first gate controlling the base resistance in response to voltage signals applied to said first gate; means for establishing electrical connections to said emitter, base, and collector regions and an active electrical connection to said first gate; a second insulation layer on the opposite side of said first semiconductor layer from said first insulation layer; a second gate on said second insulation layer separated from the bas region by said second insulation layer, said second gate comprising a doped semiconductor layer in contact with said second insulation layer and a conductive contact layer on said doped semiconductor layer, the interface between said doped semiconductor layer and said contact layer being substantially planar, said second gate controlling the base resistance independent of said first gate in response to voltage signals applied to said second gate; and means for establishing an active electrical connection to said second gate.
Claim 15
Dependent Claim
209 words
An improved, lateral bipolar transistor, comprising: a first insulation layer; a first semiconductor layer adjacent to said first insulation layer, said first semiconductor layer having emitter, base, and collector regions formed therein in a lateral bipolar transistor configuration; a first gate on said first insulation layer aligned with said base region and separated from said base region by said first insulation layer, said first gate controlling the base resistance in response to voltage signals applied to said first gate; means for establishing electrical connections to said emitter, base, and collector regions and an active electrical connection to said first gate; a second insulation layer on the opposite side of said first semiconductor layer from said first insulation layer; a second gate on said second insulation layer separated from the bas region by said second insulation layer, said second gate comprising a doped semiconductor layer in contact with said second insulation layer and a conductive contact layer on said doped semiconductor layer, the interface between said doped semiconductor layer and said contact layer being substantially planar, said second gate controlling the base resistance independent of said first gate in response to voltage signals applied to said second gate; and means for establishing an active electrical connection to said second gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |