Patent US4965816A successfully refreshed from Google Patents.
US4965816A
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Digital logic circuit for incremental encoders
Assignee: Eastman Kodak Co
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Filing: 1989-06-05
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Granted: 1990-10-23
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Expires: 2009-06-05
Abstract
Abstract A digital logic circuit for use with an incremental positioning encoder is presented. The circuit converts two quadrature pulse train signals, generated by an incremental position type encoder, to a counting CLOCK signal and an UP/DOWN count signal. The signals are transmitted on counters to generate counting clock signal and the UP/DOWN count position information. The circuit utilizes gate delays to detect the edge of a pulse train signal. No external clocks or comparators are nested. The design, by relying on the propagation delay of gates, keeps the circuit simple and more reliable.
Inventors
- 👤 Liang Shih
- 👤 Clifford L. Skillings
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:30
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/19; G05B19/21
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
194 words
A digital logic circuit for receiving a pair of quadrature phased pulse train signals indicative of position and direction of an associated member comprising: a pair of serially connected NAND and OR gates each receiving one of said quadrature phased pulse train signals for providing a two gate delay signal; a pair of exclusive-NOR gates each receiving one of said two gate delay signals with one of said quadrature phased pulse train signals to provide said pair of edge signals; an OR gate for combining said provided pair of edge signals from said pair of logic means to provide a CLOCK signal; means for receiving said pair of quadrature phase pulse train signals and said pair of edge signals from said pair of exclusive-NOR gates for converting said signals to an UP/DOWN count signal; means for providing a RESET signal; and counter means for receiving said CLOCK signal, said UP/DOWN count signal, and said RESET signal, for providing output count signals in accordance with the CLOCK signal, in a direction determined by said UP/DOWN count signal, for a duration determined by said RESET signal, indicative of the direction and position of the associated member.
Claim 2
Dependent Claim
194 words
A digital logic circuit for receiving a pair of quadrature phased pulse train signals indicative of position and direction of an associated member comprising: a pair of serially connected NAND and OR gates each receiving one of said quadrature phased pulse train signals for providing a two gate delay signal; a pair of exclusive-NOR gates each receiving one of said two gate delay signals with one of said quadrature phased pulse train signals to provide said pair of edge signals; an OR gate for combining said provided pair of edge signals from said pair of logic means to provide a CLOCK signal; means for receiving said pair of quadrature phase pulse train signals and said pair of edge signals from said pair of exclusive-NOR gates for converting said signals to an UP/DOWN count signal; means for providing a RESET signal; and counter means for receiving said CLOCK signal, said UP/DOWN count signal, and said RESET signal, for providing output count signals in accordance with the CLOCK signal, in a direction determined by said UP/DOWN count signal, for a duration determined by said RESET signal, indicative of the direction and position of the associated member.
Claim 3
Dependent Claim
189 words
A digital logic circuit for receiving a pair of quadrature phased pulse train signals indicative of position and direction of an associated member comprising: first means for receiving said pair of quadrature phased pulse train signals for converting said quadrature pulse train signals to a pair of edge signals which are combined to provide a CLOCK signal; a first gate for receiving as inputs said pair of quadrature phased pulse signals and for providing as an output a logically combined signal; a flip/flop circuit for receiving said pair of edge signals from said first means and for providing an output signal; a second logic gate for combining said logically combined signal from said first logic gate with said output signal from said flip/flop circuit to provide an UP/DOWN count signal; means for providing a RESET signal; and counter means for receiving said CLOCK signal, said UP/DOWN signal, and said RESET signal, for providing output count signals, in accordance with the CLOCK signal, in a direction determined by said UP/DOWN count signal, for a duration determined by said RESET signal, indicative of the direction and position of the associated member.
Claim 4
Dependent Claim
189 words
A digital logic circuit for receiving a pair of quadrature phased pulse train signals indicative of position and direction of an associated member comprising: first means for receiving said pair of quadrature phased pulse train signals for converting said quadrature pulse train signals to a pair of edge signals which are combined to provide a CLOCK signal; a first gate for receiving as inputs said pair of quadrature phased pulse signals and for providing as an output a logically combined signal; a flip/flop circuit for receiving said pair of edge signals from said first means and for providing an output signal; a second logic gate for combining said logically combined signal from said first logic gate with said output signal from said flip/flop circuit to provide an UP/DOWN count signal; means for providing a RESET signal; and counter means for receiving said CLOCK signal, said UP/DOWN signal, and said RESET signal, for providing output count signals, in accordance with the CLOCK signal, in a direction determined by said UP/DOWN count signal, for a duration determined by said RESET signal, indicative of the direction and position of the associated member.
Claim 5
Dependent Claim
54 words
The digital logic circuit according to claim 2 wherein said first and said second logic gates are Exclusive-NOR gates and said flip/flop circuit is a D-type flop flop having an S/ and a C/ input with one of said edge signals applied to said S/ input and other other applied to said C/ input.
Claim 6
Dependent Claim
47 words
The digital logic circuit according to claim 2 and further comprising: a third logic gate having a delay corresponding to the delay of said flip/flop circuit said third logic gate interposed between the output of said first logic gate and an input to said second logic gate.
Claim 7
Dependent Claim
58 words
The digital logic circuit according to claim 2 wherein said counter means is comprised of: four cascaded four-bit counters, each having at least an enable input for receiving said RESET signal, and UP/DOWN input for receiving said UP/DOWN signal and a CLOCK input for receiving said CLOCK signal, for providing a four-bit output indicative of the count therein.
Claim 8
Dependent Claim
43 words
The digital logic circuit according to claim 5 and further comprising: four indicating means, one each, connected to receive the four-bit output of each of said cascaded four-bit counters to provide a visual indication of the count in each of said four-bit counters.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |