US4965769A
Expired / Lapsed
US
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Semiconductor memory capable of high-speed data erasing
Assignee: Hitachi Ltd
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Filing: 1988-11-30
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Granted: 1990-10-23
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Expires: 2008-11-30
Abstract
Abstract A semiconductor memory having a plurality of word lines, and a plurality of data lines arranged to intersect the word lines. Memory cells are arranged at nodes of the word lines and the data lines. Each of the memory cells has a field effect transistor and a capacitor. A word line multiple selection circuit is provided for selecting a plurality of the word lines. The multiple selection circuit simultaneously accesses all of the memory cells by selecting all the word lines of a memory array when a semiconductor memory is in a clear mode. In the clear mode a detector selects data lines of the memory array. A plate voltage control circuit controls a voltage at one plate of each of the capacitors in the memory cells. The plate control circuit changes a voltage at the plate to a preselected clear mode voltage when a semiconductor memory is in a clear mode. It is a feature of the invention that preselected data is written in the memory cells by data communication through the data lines during the clear mode. The preselected data includes at least one "1" data of the preselected data written in the memory cells. Subsequently to end the clear mode operation, the plate voltage control circuit changes the plate voltage for normal operations.
Inventors
- 👤 Jun Etoh
- 👤 Kiyoo Itoh
- 👤 Masakazu Aoki
- 👤 Ryoichi Hori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:11
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/20; G11C11/401; G11C11/4063; G11C11/407; G11C11/4072; G11C11/408; G11C11/4087; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
195 words
A semiconductor memory comprising: a plurality of word lines; a plurality of data lines arranged to intersect said word lines; memory cells arranged at nodes of said word lines and said data lines and each having a field effect transistor and a capacitor; first means for selecting a plurality of said word lines, wherein the first means simultaneously accesses all the memory cells by selecting all word lines of an array when the semiconductor memory is in clear mode; second means for selecting a plurality of said data lines; plate voltage control means for controlling a voltage at one plate of each of the capacitors in said memory cells, wherein the plate voltage control means changes a voltage at the plate to a preselected clear mode voltage when the semiconductor memory is in clear mode and subsequently changes the plate voltage for normal operation at the end of the clear mode; writing means for writing preselected data in all the memory cells by data communication through the data lines during the clear mode, the preselected data being a logic "1" data, so as to complete the writing of a preselected data in the memory cells.
Claim 2
Dependent Claim
195 words
A semiconductor memory comprising: a plurality of word lines; a plurality of data lines arranged to intersect said word lines; memory cells arranged at nodes of said word lines and said data lines and each having a field effect transistor and a capacitor; first means for selecting a plurality of said word lines, wherein the first means simultaneously accesses all the memory cells by selecting all word lines of an array when the semiconductor memory is in clear mode; second means for selecting a plurality of said data lines; plate voltage control means for controlling a voltage at one plate of each of the capacitors in said memory cells, wherein the plate voltage control means changes a voltage at the plate to a preselected clear mode voltage when the semiconductor memory is in clear mode and subsequently changes the plate voltage for normal operation at the end of the clear mode; writing means for writing preselected data in all the memory cells by data communication through the data lines during the clear mode, the preselected data being a logic "1" data, so as to complete the writing of a preselected data in the memory cells.
Claim 3
Dependent Claim
36 words
A semiconductor memory according to claim 1, wherein storage data is written in all the memory cells after said first means selects all the word lines and after said second means selects all the data lines.
Claim 4
Dependent Claim
51 words
A semiconductor memory according to claim 1, wherein said plate voltage control means provides a first potential before storage data is written in all the memory cells and provides a second potential corresponding to at least half supply voltage after said storage data has been written in all the memory cells.
Claim 5
Dependent Claim
42 words
A semiconductor memory according to claim 1, further comprising: a common data line electrically coupled commonly with at least two of said data lines; and set circuit means for inputting erasure data to said common data line in a clear mode operation.
Claim 6
Dependent Claim
33 words
A semiconductor memory according to claim 1, wherein said second means is logically constructed to select all the data lines in response to a logical gate controlled by a clear mode control signal.
Claim 7
Dependent Claim
29 words
A semiconductor memory according to claim 1, wherein said first means includes a circuit means for driving all the word lines in response to a clear mode control signal.
Claim 8
Dependent Claim
20 words
A semiconductor memory according to claim 6, wherein said first means includes at least two bipolar transistors and CMOS transistors.
Claim 9
Dependent Claim
56 words
A semiconductor memory according to claim 7, wherein said bipolar transistors and said CMOS transistors drive said word lines in parallel so that said bipolar transistors drive said word lines at a high speed and so that said CMOS transistors drive said word lines to voltages substantially equal to a supply voltage and a ground voltage.
Claim 10
Dependent Claim
18 words
A semiconductor memory according to claim 1, wherein said plate voltage control means includes a CMOS driver circuit.
Claim 11
Dependent Claim
41 words
A semiconductor memory according to claim 1, wherein said plate voltage control means includes a CMOS circuit and a bipolar transistor, and the emitter-collector current path of the bipolar transistor is electrically connected between a plate electrode and a ground line.
Claim 12
Dependent Claim
29 words
A semiconductor memory according to claim 1, wherein said plate voltage control means includes a first circuit for normal operations, and a second circuit for the clear mode operation.
Claim 13
Dependent Claim
54 words
A semiconductor memory according to claim 1, further comprising a data input buffer for receiving input data, wherein the input buffer includes latch means for fixing the input data for the clear mode operation wherein fixing the input data comprises holding in a predetermined manner data to be used during the clear mode operation.
Claim 14
Dependent Claim
42 words
A semiconductor memory according to claim 12, further comprising: a common data line connected commonly with at least two of said data lines; and a set circuit means for inputting erasure data to said common data line in a clear mode operation.
Claim 15
Dependent Claim
53 words
A semiconductor memory according to claim 12, wherein said second means is constructed in response to a first address decoder and logical gate controlled by a clear mode control signal, and wherein said first means includes a circuit means for driving all the word lines in response to a clear mode control signal.
Claim 16
Dependent Claim
70 words
A semiconductor memory according to claim 14, wherein said first means includes at least two bipolar transistors and CMOS transistors, and wherein said bipolar transistors and said CMOS transistors drive said word lines in parallel so that said bipolar transistors drive said word lines at a high speed and so that said CMOS transistors drive said word lines to voltages substantially equal to a supply voltage and a ground voltage.
Claim 17
Dependent Claim
41 words
A semiconductor memory according to claim 14, wherein said plate voltage control means includes a CMOS circuit and a bipolar transistor, and the emitter-collector current path of the bipolar transistor is electrically coupled between a plate electrode and a ground line.
Claim 18
Dependent Claim
29 words
A semiconductor memory according to claim 14, wherein said plate voltage control means includes a first circuit for normal operation, and a second circuit for the clear mode operation.
Claim 19
Dependent Claim
55 words
A semiconductor memory according to claim 6, further comprising: data input buffer means for receiving input data, wherein the input buffer means includes latch means for fixing the input data for the clear mode operation wherein fixing the input data comprises holding in a predetermined manner data to be used during the clear mode operation.
Claim 20
Dependent Claim
51 words
A semiconductor memory according to claim 1, wherein said plate voltage control means provides ground potential before the preselected data are written in all the memory cells, and provides a potential corresponding to at least half the supply voltage after said preselected data have been written in all the memory cells.
Claim 21
Independent Claim
165 words
A method for simultaneously clearing data of a memory array, the memory array including a plurality of word lines, a plurality of data lines arranged to intersect said word lines, memory cells arranged at nodes of said word lines and said data lines and each having a field effect transistor and a capacitor, first means for selecting a plurality of said word lines, second means for selecting a plurality of said data lines, and plate voltage control means for controlling a voltage at one plate of each of the capacitors in said memory cells, the method comprising the steps of: first simultaneously accessing all the memory cells by selecting all word lines of the array; second changing a voltage at the plate to a preselected clear mode voltage; third, simultaneously writing preselected data in the memory cells by data communication through the data lines when the plate is at the preselected clear mode voltage; and, fourth subsequently changing the plate voltage for normal array operation.
Claim 22
Independent Claim
165 words
A method for simultaneously clearing data of a memory array, the memory array including a plurality of word lines, a plurality of data lines arranged to intersect said word lines, memory cells arranged at nodes of said word lines and said data lines and each having a field effect transistor and a capacitor, first means for selecting a plurality of said word lines, second means for selecting a plurality of said data lines, and plate voltage control means for controlling a voltage at one plate of each of the capacitors in said memory cells, the method comprising the steps of: first simultaneously accessing all the memory cells by selecting all word lines of the array; second changing a voltage at the plate to a preselected clear mode voltage; third, simultaneously writing preselected data in the memory cells by data communication through the data lines when the plate is at the preselected clear mode voltage; and, fourth subsequently changing the plate voltage for normal array operation.
Claim 23
Dependent Claim
18 words
The method according to claim 20 wherein the first step is controlled by a clear mode control signal.
Claim 24
Dependent Claim
26 words
The method according to claim 21 wherein the preselected clear mode voltage is 0 V, and the plate voltage for normal operation is 1/2 Vcc V.
Claim 25
Dependent Claim
30 words
The method according to claim 20 wherein the third step is completed after the first step and the second step, and the fourth step is completed after the third step.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |