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US4964946A
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Process for fabricating self-aligned field emitter arrays
Assignee: United States Department of the Navy
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Filing: 1990-02-02
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Granted: 1990-10-23
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Expires: 2010-02-02
Abstract
Abstract A process for fabricating self-aligned field emitter arrays using a self-eling planarization technique, e.g. spin-on processes, is disclosed which includes the steps of depositing a dielectric layer on top of an array of field emitters, depositing a thin conducting film over the dielectric layer, and applying a planarization layer on the thin conducting film. Thereafter the structure is selectively etched until the underlying conducting layer is exposed in regions surrounding the field emitters, thereby defining the grid apertures. The conducting layer and dielectric layer are then selectively etched sequentially to a depth sufficient to expose a field emitter cathode tip at each field emitter site. This invention uses the concept of a self-leveling, planarizing material to define the grid apertures. After defining the aperture hole size and location, then appropriate etching processes can form the apertures themselves thereby exposing the sharp field emitters which yield an integrally gridded three-dimensional field emitter array structure.
Inventors
- 👤 Henry F. Gray
- 👤 George J. Campisi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:11
CPC Classifications
H; H01; H01J; H01J9/00; H01J9/02; H01J9/022; H01J9/025
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
95 words
A process for fabricating self-aligned field emitter arrays which includes the steps of: depositing a dielectric layer on top of an array of field emitters; depositing a thin conducting film over the dielectric layer; applying a planarization layer on the thin conducting film by a self-levelling process; selectively etching the planarization layer until the underlying conducting film is exposed in regions surrounding the field emitters, thereby defining grid apertures; and selectively etching the conducting film and dielectric layer sequentially to a depth sufficient to expose a field emitter cathode tip at each field emitter site.
Claim 2
Dependent Claim
95 words
A process for fabricating self-aligned field emitter arrays which includes the steps of: depositing a dielectric layer on top of an array of field emitters; depositing a thin conducting film over the dielectric layer; applying a planarization layer on the thin conducting film by a self-levelling process; selectively etching the planarization layer until the underlying conducting film is exposed in regions surrounding the field emitters, thereby defining grid apertures; and selectively etching the conducting film and dielectric layer sequentially to a depth sufficient to expose a field emitter cathode tip at each field emitter site.
Claim 3
Dependent Claim
33 words
The process for fabricating self-aligned field emitter arrays of claim 1 which further comprises the step of covering the array of field emitters with a passivation layer, prior to depositing said dielectric layer.
Claim 4
Dependent Claim
23 words
The process for fabricating self-aligned field emitter arrays of claim 1, wherein said dielectric layer is deposited by a chemical vapor deposition technique.
Claim 5
Dependent Claim
23 words
The process for fabricating self-aligned field emitter arrays of claim 3, wherein said dielectric layer SiO 2 and is from 1-2 μm thick.
Claim 6
Dependent Claim
33 words
The process for fabricating self-aligned field emitter arrays of claim 1, wherein said thin conducting film consists of a material selected from the group consisting of Mo, W, Pt, Nb, Ta, and Al.
Claim 7
Dependent Claim
21 words
The process for fabricating self-aligned field emitter arrays of claim 5, wherein said thin conducting film is approximately 0.5 μm thick.
Claim 8
Dependent Claim
37 words
The process for fabricating self-aligned field emitter arrays of claim 1, wherein said planarization layer is applied by a spinning process and is a material selected from the group consisting of spin-on polymide, photoresist, and spin-on glass.
Claim 9
Dependent Claim
23 words
The process for fabricating self-aligned field emitter arrays of claim 2, wherein said dielectric layer is deposited by a chemical vapor deposition technique.
Claim 10
Dependent Claim
24 words
The process for fabricating self-aligned field emitter arrays of claim 8, wherein said dielectric layer is SiO 2 and is from 1-2 μm thick.
Claim 11
Dependent Claim
33 words
The process for fabricating self-aligned field emitter arrays of claim 2, wherein said thin conducting film consists of a material selected from the group consisting of Mo, W, Pt, Nb, Ta, and Al.
Claim 12
Dependent Claim
21 words
The process for fabricating self-aligned field emitter arrays of claim 10, wherein said thin conducting film is approximately 0.5 μm thick.
Claim 13
Dependent Claim
37 words
The process for fabricating self-aligned field emitter arrays of claim 11, wherein said planarization layer is applied by a spinning process and is a material selected from the group consisting of spin-on polymide, photoresist, and spin-on glass.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |