Patent US4962501A successfully refreshed from Google Patents.
US4962501A
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Bus data transmission verification system
Assignee: Unisys Corp
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Filing: 1988-09-13
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Granted: 1990-10-09
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Expires: 2008-09-13
Abstract
Abstract A plurality of transmitting and receiving elements are coupled between read and write buses. The communication paths which connects the tranmitting and receiving elements to the buses are each provided with a fault indicating circuit in series therewith. Each of said fault indicating circuits have logic gating means which include a bit register for each of the bits of a data byte and a parity bit. The output of the bit register means are coupled to isolation drivers which in turn are connected to parity checking circuits and the buses for indicating errors which occur in the bytes of a data word without degrading or delaying data transmission to and from said read and write buses.
Inventors
- 👤 Larry L. Byers
- 👤 James H. Scheuneman
- 👤 Joseba M. Desubijana
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:22
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/22; G06F11/2205; G06F11/2215
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
180 words
A bus data transmission verification system, comprising: a read data bus, a write data bus, a plurality of transmitting and receiving card elements, each being coupled between said data buses, input and output communicaiton path means coupling said card elements between said data buses, fault indicating circuit means coupled in series in said input and the output comunication paths means between each of said transmitting and receiving elements and said buses, said fault indicating circuit means comprising logic gating means for parity checking a plurality of data bytes of a data word, said logic gating means for parity checking having a plurality of parallel connected bit registers, each said bit register having a data byte input and a parity bit input connected thereto, each said logic gating means having a parity check circuit coupled to the output of each said bit register for generating error signals indicative of byte errors, and said fault indicating circuit means comprising storage means coupled to the output of said parity checking circuits for storing signals indicative of data byte errors in said data word.
Claim 2
Dependent Claim
180 words
A bus data transmission verification system, comprising: a read data bus, a write data bus, a plurality of transmitting and receiving card elements, each being coupled between said data buses, input and output communicaiton path means coupling said card elements between said data buses, fault indicating circuit means coupled in series in said input and the output comunication paths means between each of said transmitting and receiving elements and said buses, said fault indicating circuit means comprising logic gating means for parity checking a plurality of data bytes of a data word, said logic gating means for parity checking having a plurality of parallel connected bit registers, each said bit register having a data byte input and a parity bit input connected thereto, each said logic gating means having a parity check circuit coupled to the output of each said bit register for generating error signals indicative of byte errors, and said fault indicating circuit means comprising storage means coupled to the output of said parity checking circuits for storing signals indicative of data byte errors in said data word.
Claim 3
Dependent Claim
31 words
A bus data transmission system as set forth in claim 1 wherein said logic gating means further includes AND gate means coupled between said bit registers and said parity checking circuits.
Claim 4
Dependent Claim
28 words
A bus data transmission system as set forth in claim 2 wherein said AND gate means are provided with an enable input coupled to a central pipeline controller.
Claim 5
Dependent Claim
37 words
A bus data tramission system as set forth in claim 3 wherein the output of said AND gate means is coupled to an external isolation driver having its output coupled to said read or said write bus.
Claim 6
Dependent Claim
38 words
A bus data transmission system as set forth in claim 3 wherein the output of said AND gate means is coupled to an internal isolation driver having its output connected as an input to said parity checking circuit.
Claim 7
Dependent Claim
38 words
A bus data transmission system as set forth in claim 1 which further includes a central pipeline controller coupled to said fault indicating means for determining the element and type of error detected by said parity checking circuit.
References Cited (Backward Citations)
US4414669A
Cited
US4670876A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-08 | 1994-04-09 | 1994-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-08 | 1998-04-09 | 1998-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-08 | 2002-04-09 | 2002-10-09 | $7700.00 | Window Closed / Lapsed |