Parity integrity check logic

Claim 1

In a computer system having a plurality of modules including a processing module, said processing module including a plurality of circuit components, one circuit component being a CPU for executing instructions, for generating control signals, and for producing sets of binary data signals and sets of binary address signals, said sets of signals being transferred between circuit components of a module via data and address lines and between modules connected to a module bus via the module bus, the sets of data signals transmitted over the module bus and the sets of data signals from addressable circuit components of a module capable of storing sets of data bits including a parity bit associated with each such set of data bits, each module including parity error detection circuit means for checking the validity of a set of bits and the set's associated parity bit; an apparatus for verifying the operation of the parity error detection circuits comprising: parity control register means for receiving control bits and a set of data bits from the CPU and for producing in response thereto binary parity control signals and a binary enable/disable control signal under the control of the CPU; data parity and parity error check generator means operatively connected to the data lines of the processor module for receiving as inputs a set of data bits asserted on the data lines and for outputting a parity bit for the set of data bits applied during a write operation in execution by the CPU and for outputting a check bit indicating the validity of a set of data bits and the set's associated parity bit applied to the generator means when the CPU is executing a read operation; and gate means for controlling one input signal to the data parity generator, said gate means having applied to it a parity control signal from the parity control register means, a binary read/write control signal from the CPU and a parity bit associated with a set of data bits asserted on the data lines, said gate means causing the parity bit produced by the generator means to be valid if the read/write control signal has a value denoting a write operation is in process, and if the parity control signal has one value, and the parity bit produced to be invalid under the same conditions if the parity control signal has its other value, said gate means causing the check bit signal produced by the generator means to be valid if the read/write control signal has a value denoting a read operation is in execution and if the parity bit applied to the gate means is valid and for the check bit signal produced by the generator means to be invalid under the same conditions if the parity bit applied to the gate is invalid, whereby the CPU can cause the data parity and parity error check generator means to produce an invalid parity bit for a set of data bits, write that set of data bits and its invalid parity bit into an addressable location in a circuit component of the processor module, read the set of data bits and its associated parity bit from the location in which it is stored in the circuit component to check the operation of a data parity error check generator.