US4962056A
Expired / Lapsed
US
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Method of manufacturing from a semiconductor wafer a dielectric substrate including mutually insulated and separated island regions, and a method of manufacturing semiconductor elements from the dielectric substrate
Assignee: Toshiba Corp
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Filing: 1989-01-04
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Granted: 1990-10-09
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Expires: 2009-01-04
Abstract
Abstract According to the method of the present invention of manufacturing, from a semiconductor wafer, a dielectric substrate including insulated and separated island regions, a silicon oxide film is formed on a surface of a monocrystalline semiconductor wafer, and a mask consisting of a frame portion spreading on a peripheral region of the wafer and a grid-like portion arranged within the frame portion is formed. Then, in a patterning step, the surface of the wafer is exposed with the frame portion and the grid-like portion of the mask being left. Separation grooves arranged in a grid-like manner are formed in the exposed surface by etching. After a silicon oxide film is formed on the surfaces of the grooves, a polycrystalline semiconductor layer is made to grow on the silicon oxide film formed on the surfaces of the grooves and on the silicon oxide film formed on the surface of the wafer. The resultant structure is lapped from the side of the surface of the wafer such that the structure has a predetermined thickness as measured from a reference plane defined in the polycrystalline semiconductor layer, thus forming a plurality of island regions divided by the separation grooves.
Inventors
- 👤 Bunshiro Yamaki
- 👤 Nobutaka Matsuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:57
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S438/00; Y10S438/928; Y10S438/977
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
294 words
A method of manufacturing a dielectric insulated/separated substrate from a semiconductor wafer, comprising: a step of bonding a first monocrystalline semiconductor wafer and a second monocrystalline semiconductor wafer, with a first insulation film being interposed between said first and second wafers; a step of lapping the first monocrystalline semiconductor wafer by a predetermined thickness; a mask forming step of forming a mask, having a frame portion with a predetermined width arranged along a peripheral region of the first monocrystalline semiconductor wafer and a grid-like portion arranged within the frame portion, by forming a second insulation film on a surface of the first monocrystalline semiconductor wafer; a patterning step of exposing, on the basis of said mask forming step, the surface of the first monocrystalline semiconductor wafer in a grid-like manner, with the frame portion and the grid-like portion remaining; a step of forming separation grooves in a grid-like manner, to such a depth that the separation grooves reach the first insulation film, by etching the surface of the semiconductor wafer exposed in the grid-like manner by said patterning step; a step of formimg an insulation film on the surfaces of the separation grooves; a step of forming a polycrystalline semiconductor layer on said remaining frame portion arranged along the peripheral region of the first monocrystalline semiconductor wafer, and on said grid-like portion on the first monocrystalline semiconductor wafer, and further on the insulation film formed on the surfaces of the separation grooves; and a step of forming a plurality of monocrystalline island regions, into which the wafer is divided by the separation grooves formed in the grid-like manner, by lapping so as to have a predetermined thickness as measured from a reference bottom surface of one of the first and second monocrystalline semiconductor wafers.
Claim 2
Independent Claim
294 words
A method of manufacturing a dielectric insulated/separated substrate from a semiconductor wafer, comprising: a step of bonding a first monocrystalline semiconductor wafer and a second monocrystalline semiconductor wafer, with a first insulation film being interposed between said first and second wafers; a step of lapping the first monocrystalline semiconductor wafer by a predetermined thickness; a mask forming step of forming a mask, having a frame portion with a predetermined width arranged along a peripheral region of the first monocrystalline semiconductor wafer and a grid-like portion arranged within the frame portion, by forming a second insulation film on a surface of the first monocrystalline semiconductor wafer; a patterning step of exposing, on the basis of said mask forming step, the surface of the first monocrystalline semiconductor wafer in a grid-like manner, with the frame portion and the grid-like portion remaining; a step of forming separation grooves in a grid-like manner, to such a depth that the separation grooves reach the first insulation film, by etching the surface of the semiconductor wafer exposed in the grid-like manner by said patterning step; a step of formimg an insulation film on the surfaces of the separation grooves; a step of forming a polycrystalline semiconductor layer on said remaining frame portion arranged along the peripheral region of the first monocrystalline semiconductor wafer, and on said grid-like portion on the first monocrystalline semiconductor wafer, and further on the insulation film formed on the surfaces of the separation grooves; and a step of forming a plurality of monocrystalline island regions, into which the wafer is divided by the separation grooves formed in the grid-like manner, by lapping so as to have a predetermined thickness as measured from a reference bottom surface of one of the first and second monocrystalline semiconductor wafers.
Claim 3
Independent Claim
324 words
A method of manufacturing a dielectric insulated/separated substrate from a semiconductor wafer, comprising: a step of bonding a first monocrystalline semiconductor wafer and a second monocrystalline semiconductor wafer, with a first insulation film being interposed between said first and second wafers; a step of lapping the first monocrystalline semiconductor wafer by a predetermined thickness; a mask forming step of forming a mask, having a frame portion with a predetermined width arranged along a peripheral region of the first monocrystalline semiconductor wafer and a grid-like portion arranged within the frame portion, by forming a second insulation film on a surface of the first monocrystalline semiconductor wafer; a patterning step of exposing, on the basis of said mask forming step, the surface of the first monocrystalline semiconductor wafer in a grid-like manner, with the frame portion and the grid-like portion remaining; a step of forming separation grooves in a grid-like manner, to such a depth that the separation grooves reach the first insulation film, by etching the surface of the semiconductor water exposed in the grid-like manner by said patterning step; a step of forming an insulation film on the surfaces of the separation grooves; a step of forming a polycrystalline semiconductor layer on said remaining frame portion arranged along the peripheral region of the first monocrystalline semiconductor wafer, and on said grid-like portion on the first monocrystalline semiconductor wafer, and further on the insulation film formed on the surfaces of the separation grooves; a step of forming a plurality of monocrystalline island regions, into which the wafer is divided by the separation grooves formed in the grid-like manner, by lapping so as to have a predetermined thickness as measured from a reference bottom surface of one of the first and second monocrystalline semiconductor wafers; and a step of forming a semiconductor element in each of the monocrystalline semiconductor island regions, and cutting off semiconductor integrated elements formed of the island regions from the semiconductor wafer.
Claim 4
Independent Claim
324 words
A method of manufacturing a dielectric insulated/separated substrate from a semiconductor wafer, comprising: a step of bonding a first monocrystalline semiconductor wafer and a second monocrystalline semiconductor wafer, with a first insulation film being interposed between said first and second wafers; a step of lapping the first monocrystalline semiconductor wafer by a predetermined thickness; a mask forming step of forming a mask, having a frame portion with a predetermined width arranged along a peripheral region of the first monocrystalline semiconductor wafer and a grid-like portion arranged within the frame portion, by forming a second insulation film on a surface of the first monocrystalline semiconductor wafer; a patterning step of exposing, on the basis of said mask forming step, the surface of the first monocrystalline semiconductor wafer in a grid-like manner, with the frame portion and the grid-like portion remaining; a step of forming separation grooves in a grid-like manner, to such a depth that the separation grooves reach the first insulation film, by etching the surface of the semiconductor water exposed in the grid-like manner by said patterning step; a step of forming an insulation film on the surfaces of the separation grooves; a step of forming a polycrystalline semiconductor layer on said remaining frame portion arranged along the peripheral region of the first monocrystalline semiconductor wafer, and on said grid-like portion on the first monocrystalline semiconductor wafer, and further on the insulation film formed on the surfaces of the separation grooves; a step of forming a plurality of monocrystalline island regions, into which the wafer is divided by the separation grooves formed in the grid-like manner, by lapping so as to have a predetermined thickness as measured from a reference bottom surface of one of the first and second monocrystalline semiconductor wafers; and a step of forming a semiconductor element in each of the monocrystalline semiconductor island regions, and cutting off semiconductor integrated elements formed of the island regions from the semiconductor wafer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-08 | 1994-04-09 | 1994-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-08 | 1998-04-09 | 1998-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-08 | 2002-04-09 | 2002-10-09 | $7700.00 | Window Closed / Lapsed |