Digital signal processor

Claim 2

A semiconductor integrated circuit device comprising: data lines; a plurality of memory cells each having input/output terminals and a selection terminal, wherein said input/output terminals are connected to said data lines, respectively; a plurality of word lines connected to said selection terminals of said memory cells, respectively; address signal generation means for generating a second address signal different from a first address signal upon receipt of said first address signal; selection means for selecting a first word line in accordance with said first address signal upon receipt of said first address signal, and thereafter selecting a second word line in accordance with said second address signal; and, amplification means for amplifying data transmitted from a first memory cell connected to the first word line selected in accordance with said first address signal to said data lines, said amplification means being connected to said data lines; wherein the memory data of said first memory cell selected in accordance with said first address signal is written into said second memory cell connected to said second word line selected in accordance with said second address signal.

Claim 3

The semiconductor integrated circuit device according to claim 1, further comprising control means, connected to said selection means and to said amplification means, for controlling said selection means and said amplification means to select said second word line at a predetermined time during a period in which said first word line is selected and before said amplification means amplifies the data transmitted.

Claim 4

The semiconductor integrated circuit device according to claim 2, wherein said amplification means includes: a flip-flop means for storing a data bit, the flip-flop means having input/output nodes connected to said data lines; first switch means, connected between a voltage potential point and a voltage potential node of said flip-flop means and controlled by said control means, for gating said flip-flop means; and, second switch means, connected between another voltage potential point and another voltage potential node of said flip-flop means and controlled by said control means for gating said flip-flop means.

Claim 5

The semiconductor integrated circuit device according to claim 3, further comprising RAM address pointer means for generating said first address signal.

Claim 6

The semiconductor integrated circuit device according to claim 2, wherein said selection means comprises decoders having output nodes connected to a plurality of said word lines, and a selection circuit means for receiving said first and second address signal and for supplying said first and second address signal selectively to input nodes of said decoders.

Claim 7

A random access memory (RAM) device for providing access to a plurality of selected groups of memory cells in the memory device in a memory cycle comprising: a plurality of memory cells; a means for receiving a plurality of address signals, the address signals defining a first selected group of the memory cells and the address signals being received from an external source; a means for modifying the plurality of received address signals by a predetermined value, the modified address signals defining a second group of memory cells and the modifying means being operably connected to the receiving means for communicating the modified address signals to the receiving means; a means for generating an address selection signal selecting either the received address signals or the modified address signals, the generating means generating a received address selection signal followed by a modified address selection signal when the generating address selection signal means receives an external signal defining a data shift; a means for decoding the selected address signals and generating a group select signal selecting the group of memory cells defined by the selected address signals, the decoding means being interposed between the means for receiving address signals and the memory cells; a means for temporarily storing a data content of the selected group of memory cells; and, a control signal selectively enabling or disabling the decoding address signals means whereby either group of memory cells can be accessed by changing the address signals selected through the address selecting means in conjunction with the enabling and disabling of the decoding means.

Claim 8

A random access memory (RAM) device for providing access to a plurality of selected groups of memory cells in the memory device in a memory cycle comprising: a plurality of memory cells; a means for receiving a plurality of address signals, the address signals defining a first selected group of the memory cells and the address signals being received from an external source; a means for modifying the plurality of received address signals by a predetermined value, the modified address signals defining a second group of memory cells and the modifying means being operably connected to the receiving means for communicating the modified address signals to the receiving means; a means for generating an address selection signal selecting either the received address signals or the modified address signals, the generating means generating a received address selection signal followed by a modified address selection signal when the generating address selection signal means receives an external signal defining a data shift; a means for decoding the selected address signals and generating a group select signal selecting the group of memory cells defined by the selected address signals, the decoding means being interposed between the means for receiving address signals and the memory cells; a means for temporarily storing a data content of the selected group of memory cells; and, a control signal selectively enabling or disabling the decoding address signals means whereby either group of memory cells can be accessed by changing the address signals selected through the address selecting means in conjunction with the enabling and disabling of the decoding means.

Claim 9

The random access memory device according to claim 6, wherein the control signal comprises a decoding means enabling signal and a decoding means disabling signal, the decoding means enabling signal being active when the first selected group of memory cells is selected and when the modified address is selected, the decoding means disabling signal being active after the first group of memory cells is selected and before the modified address is selected.

Claim 10

The random access memory device according to claim 7, wherein the means for temporarily storing a data content comprises a means for saving the data content of the selected group of memory cells when the decoding means operates to decode the received address signal and for writing the data content into the selected group of memory cells defined by the modified address signals.

Claim 11

A random access memory device comprising: a plurality of memory cells; a means for decoding address signals received from an external source and generating a first signal designating a first plurality of memory cells; a means for generating a second signal designating a second plurality of memory cells at a predetermined time following the generation of the first designating signal; a means for temporarily storing a data content of the selected group of memory cells; and, a control signal means for enabling the first and second signals, the second signal being enabled a predetermined time after the first signal is enabled.

Claim 12

A random access memory device comprising: a plurality of memory cells; a means for decoding address signals received from an external source and generating a first signal designating a first plurality of memory cells; a means for generating a second signal designating a second plurality of memory cells at a predetermined time following the generation of the first designating signal; a means for temporarily storing a data content of the selected group of memory cells; and, a control signal means for enabling the first and second signals, the second signal being enabled a predetermined time after the first signal is enabled.

Claim 15

A random access memory device comprising: a data line; a first memory cell having a selection node and an output node coupled to said data line; a second memory cell having a selection node and an input node coupled to said data line; a first word line coupled to said selection node of said first memory cell; a second word line coupled to said selection node of said second memory cell; selection means, coupled to said first and second word lines, for generating a second selection signal to said second word line after generating a first selection signal to said first word line; amplifier means, coupled to said data line, for amplifying data provided from said first memory cell in response to a control signal; and means for transmitting the amplified data to said second memory cell, wherein said selection means includes means coupled to said amplifier means for providing said control signal to said amplifier means between the generation of said first selection signal and the generation of said second selection signal.

Claim 16

A random access memory device comprising: a data line; a first memory cell having a selection node and an output node coupled to said data line; a second memory cell having a selection node and an input node coupled to said data line; a first word line coupled to said selection node of said first memory cell; a second word line coupled to said selection node of said second memory cell; selection means, coupled to said first and second word lines, for generating a second selection signal to said second word line after generating a first selection signal to said first word line; amplifier means, coupled to said data line, for amplifying data provided from said first memory cell in response to a control signal; and means for transmitting the amplified data to said second memory cell, wherein said selection means includes means coupled to said amplifier means for providing said control signal to said amplifier means between the generation of said first selection signal and the generation of said second selection signal.

Claim 17

The random access memory device according to claim 11, wherein said selection means includes an address decoder coupled to said first and second word lines; address signal generating means, coupled to said address decoder, for generating a first address signal to select said first word line; and means, coupled to said address signal generating means and to said address decoder, for generating a second address signal to select said second word line on basis of said first address signal.

Claim 18

A semiconductor integrated circuit device comprising: a memory array means for storing data; incrementing circuit means for incrementing a value of an address pointer signal from a first address value to an incremented address value, to generate an incremented address pointer signal; unit decoder circuit means, responsive to the address pointer signal and to the incremented address pointer signal, for selecting a word line of the memory array; address select circuit means, responsive to an address shift signal, for selectively coupling the unit decoder circuit means to the address pointer signal and to the incremented address pointer signal; and, storage sense amplifier means for temporarily storing retrieved data read from an address of the memory array defined by the first address value during a read data cycle of the semiconductor integrated circuit device and for writing the retrieved data to an address of the memory array defined by the incremented address value during the read data cycle in response to the address shift signal.

Claim 19

A semiconductor integrated circuit device comprising: a memory array means for storing data; incrementing circuit means for incrementing a value of an address pointer signal from a first address value to an incremented address value, to generate an incremented address pointer signal; unit decoder circuit means, responsive to the address pointer signal and to the incremented address pointer signal, for selecting a word line of the memory array; address select circuit means, responsive to an address shift signal, for selectively coupling the unit decoder circuit means to the address pointer signal and to the incremented address pointer signal; and, storage sense amplifier means for temporarily storing retrieved data read from an address of the memory array defined by the first address value during a read data cycle of the semiconductor integrated circuit device and for writing the retrieved data to an address of the memory array defined by the incremented address value during the read data cycle in response to the address shift signal.