Adapter for attaching I/O devices to I/O communications with alternating read and write modes link

Claim 2

An adapter for interfacing a device with a serial data link comprising: a first storage means for storing data supplied from the serial data link; a second storage means for storing device data; a device address bus coupled to the second storage means; a device data bus coupled to the second storage means; a microprocessor coupled to the serial data link and for generating enabling signals; a microprocessor address bus interconnecting the first storage means and the microprocessor; a microprocessor data bus interconnecting the first storage means and the microprocessor; a first control means for controlling the flow of data between the device data bus and the microprocessor data bus; a second control means for interconnecting the microprocessor address bus and the device address bus; and a third control means responsive to the enabling signals and to generate other control signals for activating the first and second control means and for simultaneously placing the first storage means and the second storage means into respective read and write modes so that if the microprocessor executes a first command on the first storage means when it is in read mode data stored at a selected address in said first storage means is copied at an identical address in the second storage means and if the microprocessor executes the first command on the second storage means when it is in a read mode data stored at a selected address in the second storage means is copied in the first storage means.

Claim 3

The adapter of claim 1 further including means coupled to the second storage means for generating a stream of video data for displaying on a display device.

Claim 4

The adapter of claim 1 wherein the storage means includes a RAM device.

Claim 5

The adapter of claim 1 wherein the third means includes combinatorial logic circuitry for monitoring predetermined logic levels at said microprocessor and to generate a series of enabling signals.

Claim 6

A circuit arrangement for interfacing a display device with a data link comprising: a microprocessor for receiving data from the data link; said microprocessor having an output address bus, an output data bus and a plurality of control lines for transmitting control signals generated by said microprocessor; a first storage means having a first address bus connected to the output address bus and a first data bus connected to the output data bus; a second storage means for storing data for viewing on said display device; said second storage means having a second address bus and a second data bus; a multiplexor circuit means interconnecting the second address bus and the output address bus, said multiplexor circuit means when activated by enabling signals interconnects the second address bus and the output address bus so that the same locations are selected in the first and the second storage means; a transceiver circuit means interconnecting the second data bus and the output data bus, said transceiver circuit means responsive to enabling signals to cause data on the second data bus to be placed on the output data bus or data on the output data bus to be placed on the second data bus; and a control means responsive to control signals generated by the microprocessor and for generating the enabling signals and other control signals which simultaneously places the first storage means and the second storage means in opposite modes so that if the microprocessor issues a read command to the first storage means data at a selected address in the first storage means is transferred to and written at a like address in the second storage means or if the microprocessor issues a read command to the second storage means data at a selected address in the second storage means is transferred to and written at a like address in the first storage means.

Claim 7

A circuit arrangement for interfacing a display device with a data link comprising: a microprocessor for receiving data from the data link; said microprocessor having an output address bus, an output data bus and a plurality of control lines for transmitting control signals generated by said microprocessor; a first storage means having a first address bus connected to the output address bus and a first data bus connected to the output data bus; a second storage means for storing data for viewing on said display device; said second storage means having a second address bus and a second data bus; a multiplexor circuit means interconnecting the second address bus and the output address bus, said multiplexor circuit means when activated by enabling signals interconnects the second address bus and the output address bus so that the same locations are selected in the first and the second storage means; a transceiver circuit means interconnecting the second data bus and the output data bus, said transceiver circuit means responsive to enabling signals to cause data on the second data bus to be placed on the output data bus or data on the output data bus to be placed on the second data bus; and a control means responsive to control signals generated by the microprocessor and for generating the enabling signals and other control signals which simultaneously places the first storage means and the second storage means in opposite modes so that if the microprocessor issues a read command to the first storage means data at a selected address in the first storage means is transferred to and written at a like address in the second storage means or if the microprocessor issues a read command to the second storage means data at a selected address in the second storage means is transferred to and written at a like address in the first storage means.

Claim 8

The circuit arrangement set forth in claim 5 wherein the opposite modes include a write mode and a read mode.