US4559620A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mass memory system addressing circuit
Assignee: Mobil Oil AS
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Filing: 1982-09-14
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Granted: 1985-12-17
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Expires: 2002-09-14
Abstract
Abstract The interface between a computer and a solid state mass memory is provided by an electronic circuit wherein data is rearranged. Data may be received in multiplexed or unmultiplexed form. The disclosed electronic circuit assigns address locations using three parameters, a starting location parameter, an increment value parameter and an increment repetition parameter to permit nonsequential addressing or memory location skipping.
Inventors
- 👤 Ron B. Blair
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:19
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
192 words
In a bidirectional high speed data storage system wherein seismic acoustic data may be received in either multiplexed or unmultiplexed form and is written into and read out of a memory, an interface between a computer and a solid state mass memory comprising: means connected to a data source for receiving data having a plurality of data samples; means for assigning a memory address to each sample including increment means for skipping a predetermined number of memory addresses between each sample wherein said incremental means includes means for multiplexing said plurality of samples and means for demultiplexing said plurality of samples; writing means connected to the memory for writing each of said samples into a location in the memory corresponding to its assigned address; parity signal generating means connected to said writing means for writing for producing a parity bit with each of said samples; and means connected to the memory for reading said samples from the memory in a predetermined sequence, including second increment means for skipping a predetermined number of memory addresses, including means for demultiplexing said samples in said memory, and means for multiplexing said samples in said memory.
Claim 2
Dependent Claim
192 words
In a bidirectional high speed data storage system wherein seismic acoustic data may be received in either multiplexed or unmultiplexed form and is written into and read out of a memory, an interface between a computer and a solid state mass memory comprising: means connected to a data source for receiving data having a plurality of data samples; means for assigning a memory address to each sample including increment means for skipping a predetermined number of memory addresses between each sample wherein said incremental means includes means for multiplexing said plurality of samples and means for demultiplexing said plurality of samples; writing means connected to the memory for writing each of said samples into a location in the memory corresponding to its assigned address; parity signal generating means connected to said writing means for writing for producing a parity bit with each of said samples; and means connected to the memory for reading said samples from the memory in a predetermined sequence, including second increment means for skipping a predetermined number of memory addresses, including means for demultiplexing said samples in said memory, and means for multiplexing said samples in said memory.
Claim 3
Dependent Claim
29 words
The interface according to claim 1 wherein said means for receiving includes means connected to the memory for reading a previous sample from a preselected location in said memory.
Claim 4
Dependent Claim
32 words
The interface according to claim 2 wherein said means for receiving includes means for performing one function of a Boolean logic and an arithmetic function with a sample and said previous sample.
Claim 5
Dependent Claim
190 words
In a bidirectional high speed data storage system wherein data may be received in either multiplexed or unmultiplexed form and is written into and read out of a memory, an interface between a computer and a solid state mass memory comprising: means connected to a data source for receiving data having a plurality of data samples; means for assigning a memory address to each sample including increment means for skipping a predetermined number of memory addresses between each sample wherein said incremental means includes means for multiplexing said plurality of samples and means for demultiplexing said plurality of samples; writing means connected to the memory for writing each of said samples into a location in the memory corresponding to its assigned address; parity signal generating means connected to said writing means for writing for producing a parity bit with each of said samples; and means connected to the memory for reading said samples from the memory in a predetermined sequence, including second increment means for skipping a predetermined number of memory addresses, including means for demultiplexing said samples in said memory, and means for multiplexing said samples in said memory.
Claim 6
Dependent Claim
190 words
In a bidirectional high speed data storage system wherein data may be received in either multiplexed or unmultiplexed form and is written into and read out of a memory, an interface between a computer and a solid state mass memory comprising: means connected to a data source for receiving data having a plurality of data samples; means for assigning a memory address to each sample including increment means for skipping a predetermined number of memory addresses between each sample wherein said incremental means includes means for multiplexing said plurality of samples and means for demultiplexing said plurality of samples; writing means connected to the memory for writing each of said samples into a location in the memory corresponding to its assigned address; parity signal generating means connected to said writing means for writing for producing a parity bit with each of said samples; and means connected to the memory for reading said samples from the memory in a predetermined sequence, including second increment means for skipping a predetermined number of memory addresses, including means for demultiplexing said samples in said memory, and means for multiplexing said samples in said memory.
Claim 7
Dependent Claim
29 words
The interface according to claim 4 wherein said means for receiving includes means connected to the memory for reading a previous sample from a preselected location in said memory.
Claim 8
Dependent Claim
32 words
The interface according to claim 5 wherein said means for receiving includes means for performing one function of a Boolean logic and an arithmetic function with a sample and said previous sample.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-16 | 1989-06-17 | 1989-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-16 | 1993-06-17 | 1993-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-16 | 1997-06-17 | 1997-12-17 | $7700.00 | Window Closed / Lapsed |