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US4958322A
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Semiconductor pseudo memory module
Assignee: Mitsubishi Electric Corp
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Filing: 1989-07-06
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Granted: 1990-09-18
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Expires: 2009-07-06
Abstract
Abstract A semiconductor pseudo memory module includes a multilayer wiring substrate on the surface of which a plurality of DRAMs are provided and on the reverse side of which semiconductor devices of the DRAM controller and multiplexers are provided, these devices being electrically connectetd with one another by a wiring layer. The address signals supplied from outside are converted into column address signals and row address signals by the multiplexer so as to be supplied to each DRAM. Responsive to control signals supplied from outside, the DRAM controller generates a refresh signals for refreshing the DRAMS, which signal is supplied to the DRAM. In this manner, the DRAM may be used as the SRAM.
Inventors
- 👤 Ryuichi Kosugi
- 👤 Tsugio Tabaru
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:56
CPC Classifications
G; G11; G11C; G11C5/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; H; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/141; H05K1/18; H05K1/181
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
120 words
A semiconductor pseudo memory module in which functions of a static random access memory are provided by a dynamic random access memory, comprising: a multilayer wiring substrate having external connection terminals; a plurality of dynamic random access memory devices mounted on said substrate; a semiconductor multiplexing device mounted on said substrate for converting address signals applied to said connection terminals into address signals compatible to said dynamic random access memory devices; and a semiconductor refresh control device mounted on said substrate and responsive to signals applied to said external dynamic random access memory; at least two of said dynamic random access memory devices, said multiplexing device and said refresh control device being interconnected through multiple wiring layers of said substrate.
Claim 2
Dependent Claim
120 words
A semiconductor pseudo memory module in which functions of a static random access memory are provided by a dynamic random access memory, comprising: a multilayer wiring substrate having external connection terminals; a plurality of dynamic random access memory devices mounted on said substrate; a semiconductor multiplexing device mounted on said substrate for converting address signals applied to said connection terminals into address signals compatible to said dynamic random access memory devices; and a semiconductor refresh control device mounted on said substrate and responsive to signals applied to said external dynamic random access memory; at least two of said dynamic random access memory devices, said multiplexing device and said refresh control device being interconnected through multiple wiring layers of said substrate.
Claim 3
Dependent Claim
40 words
The semiconductor pseudo memory module according to claim 1, wherein said dynamic random access memory devices are mounted on one side of said substrate, and said multiplexing and refresh control devices are mounted on the opposite side of said substrate.
Claim 4
Dependent Claim
47 words
The semiconductor pseudo memory module according to claim 2, wherein said dynamic random access memory includes a plurality of elements, and wherein said semiconductor device for converting address signals includes a device for commonly supplying column address signals and row address signals to said plurality of elements.
Claim 5
Dependent Claim
62 words
The semiconductor pseudo memory module according to claim 1, wherein said multilayer wiring substrate includes a power source layer, a wiring layer, a grounding layer and an insulating layer for insulating each of these layers, and if necessary, for components for electrically connecting said wiring layer and said grounding layer and for electrically connecting said power source layer and said wiring layer.
References Cited (Backward Citations)
US4811078A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-17 | 1994-03-19 | 1994-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-17 | 1998-03-19 | 1998-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-17 | 2002-03-19 | 2002-09-18 | $7700.00 | Window Closed / Lapsed |