Patent US4956815A successfully refreshed from Google Patents.
US4956815A
Expired / Lapsed
US
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Memory cell with increased stability
Assignee: Texas Instruments Inc
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Filing: 1988-09-30
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Granted: 1990-09-11
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Expires: 2008-09-30
Abstract
Abstract A memory cell is disclosed which operates in two stable states and where an asymmetry in current through the cell is required to change the state of the cell. The cell includes a current compensating device that supplies current under ionizing radiation in a direction that is opposite to that required to write into the cell.
Inventors
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:22
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/005; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
147 words
A bi-stable logic device comprising: a set of cross-coupled inverters, said set of inverters including first and second inverters; a pair of transistors connected to the cross-coupling of the inverters so as to provide a time delay in effecting voltage changes at selected nodes within the cell via an impedance path through said transistors which lies between said selected nodes, each of said transistors including a gate, first and second terminals, the gate of a first transistor of said pair being connected to said first terminal of a second transistor of said pair in addition to the gate of a second transistor of said pair being connected to a first terminal of said first transistor; and a current compensation device, connected to each inverter, operable to supply current in response to ionizing radiation in a direction opposite to that required to change the state of the device.
Claim 2
Dependent Claim
147 words
A bi-stable logic device comprising: a set of cross-coupled inverters, said set of inverters including first and second inverters; a pair of transistors connected to the cross-coupling of the inverters so as to provide a time delay in effecting voltage changes at selected nodes within the cell via an impedance path through said transistors which lies between said selected nodes, each of said transistors including a gate, first and second terminals, the gate of a first transistor of said pair being connected to said first terminal of a second transistor of said pair in addition to the gate of a second transistor of said pair being connected to a first terminal of said first transistor; and a current compensation device, connected to each inverter, operable to supply current in response to ionizing radiation in a direction opposite to that required to change the state of the device.
Claim 3
Dependent Claim
50 words
A bi-stable logic device as recited in claim 1 wherein said second terminal of said first transistor of said pair is connected to the input of said first inverter and wherein said first terminal of said first transistor of said pair is connected to the output of said second inverter.
Claim 4
Dependent Claim
50 words
A bi-stable logic device as recited in claim 2 wherein said second terminal of said second transistor of said pair is connected to said input of said second inverter and wherein said first terminal of said second transistor of said pair is connected to said output of said first inverter.
Claim 5
Dependent Claim
50 words
A bi-stable logic device as recited in claim 1 wherein said second terminal of said first transistor of said pair is connected to the output of said first inverter and wherein said first terminal of said first transistor of said pair is connected to the input of said second inverter.
Claim 6
Dependent Claim
47 words
A bi-stable logic device as recited in claim 4 wherein said second terminal of said second transistor is connected to said output of said second inverter and wherein said first terminal of said second transistor of said pair is connected to said input of said first inverter.
Claim 7
Dependent Claim
19 words
A bi-stable logic device as recited in claim 1 wherein said transistors are metal oxide semiconductor field effect transistors.
Claim 8
Dependent Claim
20 words
A bi-stable logic device as recited in claim 1 wherein each inverter includes a p-channel transistor and a n-channel transistor.
Claim 9
Dependent Claim
36 words
A bi-stable logic device as recited in claim 1 wherein said current compensation device comprises a plurality of depletion mode transistors, each depletion mode transistor being associated with and connected to at lest one said inverter.
Claim 10
Dependent Claim
17 words
A bi-stable logic device as recited in claim 8 wherein said depletion mode transistors are p-channel transistors.
Claim 11
Dependent Claim
46 words
A bi-stable logic device as recited in claim 1 wherein said current compensation device comprises a plurality of p-channel transistors with each said p-channel transistor being connected to the output of an associated inverter, the source and drain of each said p-channel transistor being connected together.
Claim 12
Dependent Claim
99 words
A bi-stable logic device as recited in claim 1 wherein said logic device is operable in connection with pass transistors capable of passing data into and out of said bi-stable logic device, said bi-stable logic device further comprising a first p-channel transistor and a second p-channel transistor connected in series, the gate of said first p-channel transistor being connected to the gate of an associated pass transistor, the gate of said second p-channel transistor being connected to the input of an associated inverter, said source of said second p-channel transistor being connected to the output of said associated inverter.
Claim 13
Dependent Claim
100 words
A bi-stable logic device as recited in claim 1 wherein said logic device is operable in connection with pass transistors capable of passing data into and out of said bi-stable logic device, said bi-stable logic device further comprising a first n-channel transistor and a second n-channel transistor being connected to the gate of said first n-channel transistor being connected to the gate of an associated pass transistor the gate of said second n-channel transistor being connected to the input of an associated inverter, and said source of said second n-channel transistor being connected to the output of an associated inverter.
References Cited (Backward Citations)
US4638463A
Cited
US4725981A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-10 | 1994-03-12 | 1994-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-10 | 1998-03-12 | 1998-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-10 | 2002-03-12 | 2002-09-11 | $7700.00 | Window Closed / Lapsed |