Patent US4956814A successfully refreshed from Google Patents.
US4956814A
Expired / Lapsed
US
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Memory cell with improved single event upset rate reduction circuitry
Assignee: Texas Instruments Inc
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Filing: 1988-09-30
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Granted: 1990-09-11
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Expires: 2008-09-30
Abstract
Abstract The rate of single event upset in a memory cell due to energetic particle hits on a p-channel device is reduced by a pair of active devices in the cross-coupling between a pair of inverters. The active devices are controlled by voltages internal to the memory cell such that writing into the cell is not slowed significantly. Additionally, means such as a resistor or transistor are disclosed which reduce the rate of single event upset due to energetic particle hits on a n-channel device.
Inventors
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:57
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125; G11C5/00; G11C5/005
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
181 words
A bi-stable logic device comprising: a set of cross-couple inverters, said set of inverters including first and second inverters, each inverter including a n-channel transistor and a p-channel transistor, the gate of the n-channel transistor being connected to the gate of the p-channel transistor; a device connected to and between the drains of said p-channel and n-channel transistors of at least one inverter, said device being capable of providing at least a selected level of impedance between said drains of said p-channel and n-channel transistors; and a pair of transistors, each having a gate, first and second terminals, connected to the cross-coupling of the inverters so as to provide a time delay in effecting voltage changes at selected nodes within the cell via an impedance path through said pair of transistors which lies between said selected nodes, the gate of a first transistor of said pair being connected to a first terminal of a second transistor of said pair in addition to the gate of a second transistor of said pair being connected to a first terminal of said first transistor.
Claim 2
Dependent Claim
181 words
A bi-stable logic device comprising: a set of cross-couple inverters, said set of inverters including first and second inverters, each inverter including a n-channel transistor and a p-channel transistor, the gate of the n-channel transistor being connected to the gate of the p-channel transistor; a device connected to and between the drains of said p-channel and n-channel transistors of at least one inverter, said device being capable of providing at least a selected level of impedance between said drains of said p-channel and n-channel transistors; and a pair of transistors, each having a gate, first and second terminals, connected to the cross-coupling of the inverters so as to provide a time delay in effecting voltage changes at selected nodes within the cell via an impedance path through said pair of transistors which lies between said selected nodes, the gate of a first transistor of said pair being connected to a first terminal of a second transistor of said pair in addition to the gate of a second transistor of said pair being connected to a first terminal of said first transistor.
Claim 3
Dependent Claim
50 words
A bi-stable logic device as recited in claim 1 wherein said second terminal of said first transistor of said pair is connected to the input of said first inverter and wherein said first terminal of said first transistor of said pair is connected to the output of said second inverter.
Claim 4
Dependent Claim
50 words
A bi-stable logic device as recited in claim 2 wherein said second terminal of said second transistor of said pair is connected to said input of said second inverter and wherein said first terminal of said second transistor of said pair is connected to said output of said first inverter.
Claim 5
Dependent Claim
50 words
A bi-stable logic device as recited in claim 1 wherein said second terminal of said first transistor of said pair is connected to the output of said first inverter and wherein said first terminal of said first transistor of said pair is connected to the input of said second inverter.
Claim 6
Dependent Claim
47 words
A bi-stable logic device as recited in claim 4 wherein said second terminal of said second transistor is connected to said output of said second inverter and wherein said first terminal of said second transistor of said pair is connected to said input of said first inverter.
Claim 7
Dependent Claim
19 words
A bi-stable logic device as recited in claim 1 wherein said field effect transistors are metal oxide semiconductor transistors.
Claim 8
Dependent Claim
27 words
A bi-stable logic device as recited in claim 1 wherein said device connected to and between the drains of said p-channel and n-channel transistors is a resistor.
Claim 9
Dependent Claim
27 words
A bi-stable logic device as recited in claim 1 wherein said device connected to and between the drains of said p-channel and n-channel transistors is a transistor.
Claim 10
Dependent Claim
18 words
A bi-stable logic device as recited in claim 1 wherein said transistors of said pair are p-channel transistors.
Claim 11
Dependent Claim
28 words
A bi-stable logic device as recited in claim 9 wherein said transistor connected to and between the drains of said p-channel and n-channel transistors is an n-channel transistor.
Claim 12
Dependent Claim
18 words
A bi-stable logic device as recited in claim 1 wherein said transistors of said pair are n-channel transistors.
Claim 13
Dependent Claim
28 words
A bi-stable logic device as recited in claim 11 wherein said transistor connected to and between the drains of said p-channel and n-channel transistors is a p-channel transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-10 | 1994-03-12 | 1994-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-10 | 1998-03-12 | 1998-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-10 | 2002-03-12 | 2002-09-11 | $7700.00 | Window Closed / Lapsed |