Circuitry for character translate functions

Claim 2

Character translate circuitry external to a central processing unit (CPU) for enabling character translation functions, wherein the CPU performs functions on data characters in response to referenced program instructions retrieved by the CPU from a main memory storage element, and wherein the CPU includes an arithmetic logic unit for performing the functions on the data characters, at least one internal storage register for storing a data character, a data bus for transmitting and receiving data characters, and an address bus connected between the CPU and the main memory storage element for providing referenced program instruction addresses to the main memory storage element, and wherein each referenced program instruction address includes an instruction address program comprising the data character stored in the at least one internal storage register, the character translate circuitry comprising: (a) a character translation storage unit comprising a plurality of translation character storage locations and including address input means responsive to a translation storage location address for accessing a corresponding translation character storage location; and (b) access means connected between the address bus and the character translation storage unit for providing the instruction address portion to the address input means as the storage location address, wherein the address bus comprises a most significant bit set and a low order bit set and the address input means comprises a least significant bit set and a remaining bit set, the most significant bit set being connected to the least significant bit set, the low order bit set being connected to the remaining bit set, the most significant bit set corresponding to the instruction address portion, and wherein the translation character storage locations are divided into a plurality of tables, a table to be accessed being selected by the low order bit set, selection of the translation character storage location within the selected table being determined by the most significant bit set.

Claim 3

Character translate circuitry as in claim 1 wherein the remaining bit set as well as control signals issued by the CPU are decoded by address and control decode logic connected between the CPU and the character translation storage unit to provide device selection for the translation character storage unit.

Claim 4

Character translate circuitry as in claim 2 wherein the data bus of the CPU is connected directly to a data bus of the translation character storage unit for transfer of data characters between the translation character storage unit and the CPU.

Claim 5

Character translate circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters in response to program instructions retrieved by the CPU from a main memory storage element, and wherein the CPU includes an arithmetic logic unit for performing the functions on the data characters, at least one internal storage register for storing a data character, a data bus for transmitting and receiving data characters, and an address bus connected between the CPU and the main memory storage element for providing referenced program instruction addresses for retrieval from the main memory storage element, and wherein

Claim 6

Character translate circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters in response to program instructions retrieved by the CPU from a main memory storage element, and wherein the CPU includes an arithmetic logic unit for performing the functions on the data characters, at least one internal storage register for storing a data character, a data bus for transmitting and receiving data characters, and an address bus connected between the CPU and the main memory storage element for providing referenced program instruction addresses for retrieval from the main memory storage element, and wherein

Claim 7

Character translate circuitry as in claim 4 wherein the data character stored in the at least one internal register comprises a character from a first code set and the data character stored in the corresponding data character storage location comprises a character from a second code set, the character from the second code set being a translated equivalent of the character from the first code set.

Claim 8

Character translate circuitry as in claim 4 wherein the data character stored in the at least one internal register comprises a control character and the data character stored in the corresponding data character storage location comprises a character indicative of whether the control character requires special handling of the CPU.

Claim 9

Character translate circuitry as in claim 4 wherein the data character stored in the corresponding data character storage location comprises the address of a subroutine for processing the data character stored in the at least one internal storage register.

Claim 10

Character translate circuitry as in claim 7 wherein the contents of the corresponding data character storage location stores an address of a subroutine that stores the data character stored in the at least one internal register.

Claim 11

Character translate circuitry as in claim 7 wherein the data character stored in the internal storage register comprises a control character and the translation data character stored in the corresponding translation character storage location in the data character storage unit is an address of a subroutine for performing necessary control functions associated with the control character.

Claim 12

Character translate circuitry as in claim 4 wherein the translation data character stored in the corresponding data character storage is an address of a program routine for processing the data character stored in the internal storage register.

Claim 13

Character translate circuitry as in claim 4 and wherein the address bus comprises a multiple bit bus including a first bit set and a second bit set and the address input means comprises a plurality of input pins including a first pin set and a second pin set, the first bit set being connected to the second pin set, the second bit set being connected to the first pin set, the first bit set corresponding to the instruction address portion.

Claim 14

Character translate circuitry as in claim 4 wherein the address bus comprises a most significant bit set and a low order bit set and the address input means comprises a least significant bit set and a remaining bit set, the most significant bit set being connected to the least significant bit set, the low order bit set being connected to the remaining bit set, the most significant bit set corresponding to the instruction address portion.

Claim 15

Circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters based upon a set of program instructions received from a main memory storage element and includes an arithmetic logic unit for perfomring the functions on the data characters, at least one internal storage register for storing data characters, a data bus booth for transferring data characters internally within the CPU and for transmitting data characters to and receiving data characters from devices external to the CPU, and an address bus for providing addresses of referenced program instructions for retrieval from the main memory storage element, and wherein the contents of the at least one internal storage register form a portion of the address of the referenced program instruction provided on the address bus, the circuitry comprising: (a) a storage register for storing information which can be written from the CPU such that the information stored in the internal storage register may be set to a desired value by the CPU; (b) a storage unit which includes a plurality of data character storage locations which are accessed by storage unit input addresses; (c) means for exclusive ORing the data character stored in the internal storage register and the information stored in the storage register, the result of the exclusive OR being a storage unit address for accessing a corresponding storage location in the storage unit, the contents of which are provided both to the CPU to replace the data character stored in the internal storage register and to the storage register to replace the information stored in the storage register.

Claim 16

Circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters based upon a set of program instructions received from a main memory storage element and includes an arithmetic logic unit for perfomring the functions on the data characters, at least one internal storage register for storing data characters, a data bus booth for transferring data characters internally within the CPU and for transmitting data characters to and receiving data characters from devices external to the CPU, and an address bus for providing addresses of referenced program instructions for retrieval from the main memory storage element, and wherein the contents of the at least one internal storage register form a portion of the address of the referenced program instruction provided on the address bus, the circuitry comprising: (a) a storage register for storing information which can be written from the CPU such that the information stored in the internal storage register may be set to a desired value by the CPU; (b) a storage unit which includes a plurality of data character storage locations which are accessed by storage unit input addresses; (c) means for exclusive ORing the data character stored in the internal storage register and the information stored in the storage register, the result of the exclusive OR being a storage unit address for accessing a corresponding storage location in the storage unit, the contents of which are provided both to the CPU to replace the data character stored in the internal storage register and to the storage register to replace the information stored in the storage register.

Claim 17

Character translate circuitry as in claim 13 wherein the storage register is a single character storage register.

Claim 18

Character translate circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters in response to referenced program instructions retrieved by the CPU from a main memory storage element, and wherein the CPU includes an arithmetic logic unit for performing the functions on the data characters, at least one internal storage register for storing a data character, a data bus for transmitting and receiving data characters, and an address bus connected between the CPU and the main memory storage element for providing referenced program instruction addresses to the main memory storage element, and wherein each referenced program instruction address includes an instruction address portion comprising the data character stored in the at least one internal storage register, the character translate circuitry comprising: (a) a character translation storage unit comprising a plurality of translation character storage locations and including address input means responsive to a translation storage location address for accessing a corresponding translation character storage location; and (b) access means connected between the address bus and the character translation storage unit for providing the instruction address portion to the address input means as the storage location address, wherein the data character storage locations of the data character storage unit are organized as a plurality of tables, each table representing a class of data character, and wherein the tables are state transition tables such that a storage location in a table accessed by the data character stored in the at least one internal storage register corresponds to the identity of a next state and an address of a routine to be executed as the next state is entered.

Claim 19

Character translate circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters in response to referenced program instructions retrieved by the CPU from a main memory storage element, and wherein the CPU includes an arithmetic logic unit for performing the functions on the data characters, at least one internal storage register for storing a data character, a data bus for transmitting and receiving data characters, and an address bus connected between the CPU and the main memory storage element for providing referenced program instruction addresses to the main memory storage element, and wherein each referenced program instruction address includes an instruction address portion comprising the data character stored in the at least one internal storage register, the character translate circuitry comprising: (a) a character translation storage unit comprising a plurality of translation character storage locations and including address input means responsive to a translation storage location address for accessing a corresponding translation character storage location; and (b) access means connected between the address bus and the character translation storage unit for providing the instruction address portion to the address input means as the storage location address, wherein the data character storage locations of the data character storage unit are organized as a plurality of tables, each table representing a class of data character, and wherein the tables are state transition tables such that a storage location in a table accessed by the data character stored in the at least one internal storage register corresponds to the identity of a next state and an address of a routine to be executed as the next state is entered.

Claim 20

Character translate circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters in response to referenced program instructions retrieved by the CPU from a main memory storage element, and wherein the CPU includes an arithmetic logic unit for performing the functions on the data characters, at least one internal storage register for storing a data character, a data bus for transmitting and receiving data characters, and an address bus connected between the CPU and the main memory storage element for providing referenced program instruction addresses to the main memory storage element, and wherein each referenced program instruction address includes an instruction address portion comprising the data character stored in the at least one internal storage register, the character translate circuitry comprising: (a) a character translation storage unit comprising a plurality of translation character storage locations and including address input means responsive to a translation storage location address for accessing a corresponding translation character storage location; and (b) access means connected between the address bus and the character translation storage unit for providing the instruction address portion to the address input means as the storage location address, wherein the data character storage locations in the data character storage unit are organized as a plurality of tables, each table representing a class of data character, and wherein the data character stored in the at least one internal storage register accesses a storage location in each of two tables, the storage location of a first addressed table containing a length of a string that will be substituted for the data character stored in the at least one internal storage register, the storage location of a second addressed table containing the value of the substitute string, such that the data character stored in the at least one internal storage register is replaced by a variable-length string.

Claim 21

Character translate circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters in response to referenced program instructions retrieved by the CPU from a main memory storage element, and wherein the CPU includes an arithmetic logic unit for performing the functions on the data characters, at least one internal storage register for storing a data character, a data bus for transmitting and receiving data characters, and an address bus connected between the CPU and the main memory storage element for providing referenced program instruction addresses to the main memory storage element, and wherein each referenced program instruction address includes an instruction address portion comprising the data character stored in the at least one internal storage register, the character translate circuitry comprising: (a) a character translation storage unit comprising a plurality of translation character storage locations and including address input means responsive to a translation storage location address for accessing a corresponding translation character storage location; and (b) access means connected between the address bus and the character translation storage unit for providing the instruction address portion to the address input means as the storage location address, wherein the data character storage locations in the data character storage unit are organized as a plurality of tables, each table representing a class of data character, and wherein the data character stored in the at least one internal storage register accesses a storage location in each of two tables, the storage location of a first addressed table containing a length of a string that will be substituted for the data character stored in the at least one internal storage register, the storage location of a second addressed table containing the value of the substitute string, such that the data character stored in the at least one internal storage register is replaced by a variable-length string.

Claim 22

Character translate circuitry as in claim 16 wherein storage locations in the data character storage unit are organized as a plurality of state transition tables, each state representing a different number of bits of space in an output character to which the substitute strings are added, the value of the first addressed table being used to select a routine to add a number of bits to the output character and the next state corresponding to the amount of space left afterwards.

Claim 23

Circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters based upon a set of program instructions retrieved from a main memory storage element and includes a first arithmetic logic unit for performing the functions on the data characters, at least one internal storage unit for storing data characters, a data bus for both transferring data characters internally within the CPU and for transmitting data characters to and receiving data characters from devices external to the CPU, and an address bus for providing addresses of referenced program instructions for retrieval from the main memory storage element, and wherein the data character stored in the internal storage register forms a portion of the address of the referenced program instruction provided on the address bus, the circuitry comprising: (a) a storage register for storing information which can be written from the CPU such that the information stored in the storage register may be set to a desired value by the CPU; (b) a storage unit which includes a plurality of character storage locations which are accessed by storage unit input addresses; (c) logic means for receiving the data character stored in the internal storage register and information stored in the storage register as inputs and which provides a storage unit input address as an output, the storage unit input address being used to access a storage location in the storage unit, the data character stored in the storage location being provided both to the CPU to replace the data character stored in the internal storage register and to the storage register to replace the information stored in the storage register.

Claim 24

Circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters based upon a set of program instructions retrieved from a main memory storage element and includes a first arithmetic logic unit for performing the functions on the data characters, at least one internal storage unit for storing data characters, a data bus for both transferring data characters internally within the CPU and for transmitting data characters to and receiving data characters from devices external to the CPU, and an address bus for providing addresses of referenced program instructions for retrieval from the main memory storage element, and wherein the data character stored in the internal storage register forms a portion of the address of the referenced program instruction provided on the address bus, the circuitry comprising: (a) a storage register for storing information which can be written from the CPU such that the information stored in the storage register may be set to a desired value by the CPU; (b) a storage unit which includes a plurality of character storage locations which are accessed by storage unit input addresses; (c) logic means for receiving the data character stored in the internal storage register and information stored in the storage register as inputs and which provides a storage unit input address as an output, the storage unit input address being used to access a storage location in the storage unit, the data character stored in the storage location being provided both to the CPU to replace the data character stored in the internal storage register and to the storage register to replace the information stored in the storage register.

Claim 25

Circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters based upon a set of program instructions retrieved from a main memory storage element and includes an arithmetic logic unit for performing the functions on the data characters, at least one multiple-character internal storage register for storing data characters, a data bus both for transferring data characters internally within the CPU and for transmitting data characters to and receiving data characters from devices external to the CPU, and an address bus for providing addresses of referenced program instructions for retrieval from the main memory storage element, and wherein the contents of the at least one internal storage register form a portion of the address of the referenced program instruction provided on the address bus, the circuitry comprising: (a) a storage register for storing information which can be written from the CPU such that the internal storage register may be set to a desired value by the CPU; (b) a storage unit which includes a plurality of data character storage locations which are accessed by storage unit input addresses; (c) means for exclusive ORing the data character stored in the internal storage register and the information stored in the storage register, the result of the exclusive OR being a storage unit address utilizable for accessing a corresponding storage location in the storage unit, the contents of which are provided both to the CPU to replace the data character stored in the internal storage register, the information stored in the accessed storage location also being provided to the storage register to replace contents of the storage register; and (d) a latch located between the output of the exclusive OR means and the address inputs of the storage unit for maintaining the stability of the storage unit input address even though the contents of the storage register may be changing.

Claim 26

Circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters based upon a set of program instructions retrieved from a main memory storage element and includes an arithmetic logic unit for performing the functions on the data characters, at least one multiple-character internal storage register for storing data characters, a data bus both for transferring data characters internally within the CPU and for transmitting data characters to and receiving data characters from devices external to the CPU, and an address bus for providing addresses of referenced program instructions for retrieval from the main memory storage element, and wherein the contents of the at least one internal storage register form a portion of the address of the referenced program instruction provided on the address bus, the circuitry comprising: (a) a storage register for storing information which can be written from the CPU such that the internal storage register may be set to a desired value by the CPU; (b) a storage unit which includes a plurality of data character storage locations which are accessed by storage unit input addresses; (c) means for exclusive ORing the data character stored in the internal storage register and the information stored in the storage register, the result of the exclusive OR being a storage unit address utilizable for accessing a corresponding storage location in the storage unit, the contents of which are provided both to the CPU to replace the data character stored in the internal storage register, the information stored in the accessed storage location also being provided to the storage register to replace contents of the storage register; and (d) a latch located between the output of the exclusive OR means and the address inputs of the storage unit for maintaining the stability of the storage unit input address even though the contents of the storage register may be changing.

Claim 27

Circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters based upon a set of program instructions retrieved from a main memory storage element and includes an arithmetic logic unit for performing the functions on the data characters, at least one multiple-character internal storage unit for storing data characters, a data bus for both transferring data characters internally within the CPU and for transmitting data characters to and receiving data characters from devices external to the CPU, and an address bus for providing addresses of referenced program instructions for retrieval from the main memory storage element, and wherein the data character stored in the internal storage unit forms a portion of the address of the referenced program instruction available on the address bus, the circuitry comprising: (a) a storage register for storing information which can be written from the CPU such that the contents of the storage register may be set to a desired value by the CPU; (b) a storage unit which includes a plurality of data character storage locations which are accessed by storage unit input addresses; (c) logic means for receiving the data character stored in the internal storage register and the information stored in the storage register as inputs and which provides a storage unit input address as an output, the storage unit input address being used to access a storage location in the storage unit, the data character stored in the storage location being provided to the CPU to replace data characters stored in the internal storage unit and also to the storage register to replace the information stored in the storage register; and (d) a latch located between the output of the logic means and the address inputs of the storage unit for maintaining the stability of the storage unit input address even though the contents of the storage register may be changing.

Claim 28

Circuitry external to a central processing unit (CPU) for enabling data character translation functions, wherein the CPU performs functions on data characters based upon a set of program instructions retrieved from a main memory storage element and includes an arithmetic logic unit for performing the functions on the data characters, at least one multiple-character internal storage unit for storing data characters, a data bus for both transferring data characters internally within the CPU and for transmitting data characters to and receiving data characters from devices external to the CPU, and an address bus for providing addresses of referenced program instructions for retrieval from the main memory storage element, and wherein the data character stored in the internal storage unit forms a portion of the address of the referenced program instruction available on the address bus, the circuitry comprising: (a) a storage register for storing information which can be written from the CPU such that the contents of the storage register may be set to a desired value by the CPU; (b) a storage unit which includes a plurality of data character storage locations which are accessed by storage unit input addresses; (c) logic means for receiving the data character stored in the internal storage register and the information stored in the storage register as inputs and which provides a storage unit input address as an output, the storage unit input address being used to access a storage location in the storage unit, the data character stored in the storage location being provided to the CPU to replace data characters stored in the internal storage unit and also to the storage register to replace the information stored in the storage register; and (d) a latch located between the output of the logic means and the address inputs of the storage unit for maintaining the stability of the storage unit input address even though the contents of the storage register may be changing.