US4956688A
Expired / Lapsed
US
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Radiation resistant bipolar memory
Assignee: Hitachi Ltd
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Filing: 1989-06-27
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Granted: 1990-09-11
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Expires: 2009-06-27
Abstract
Abstract A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are inverted, and the load device thereof has a shielding arrangement for shielding the flip flop from the noise produced within the substrate. Either pnp type transistors or Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in the region where the device is provided. A reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.
Inventors
- 👤 Noriyuki Honma
- 👤 Tohru Nakamura
- 👤 Kazuo Nakazato
- 👤 Motoaki Matsumoto
- 👤 Tetsuya Hayashida
- 👤 Masaharu Kubo
- 👤 Kazuhiko Sagara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:28
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/10; H10D; H10D10/00; H10D10/40; H10D10/461
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
284 words
A semiconductor memory comprising: a semiconductor substrate; memory cells, each of which comprises first and second transistors formed on the semiconductor substrate and first and second load devices formed on the semiconductor substrate; upper and lower word lines for selecting the memory cells; bit lines for reading and writing information of the memory cells; and coupling devices for electrically interconnecting the bit lines and the memory cells, wherein buried layers of the first and second transistors are isolated from the buried layers of the first and second load devices and/or from buried layers of the coupling devices, and wherein the first and second transistors employ the buried layers as emitters, respectively, wherein each memory cell is constructed by interconnecting a base of said first transistor and a collector of said second transistor and interconnecting a collector of said first transistor and a base of said second transistor, said load devices are first and second pnp transistors, a collector of said first pnp transistor is connected to a base of said first transistors and a collector of said second transistor, a collector of said second pnp transistor is connected to a base of said second transistor and a collector of said first transistor, and emitters of said first and second pnp transistors are electrically connected to said upper word line, wherein a base of the first pnp transistor is connected to a collector of the first transistor and the base of the second transistor, wherein a base of the second pnp transistor is connected to a collector of the second transistor and the base of the first transistor, and wherein emitters of said first and second transistors are electrically connected to the lower word line.
Claim 2
Dependent Claim
284 words
A semiconductor memory comprising: a semiconductor substrate; memory cells, each of which comprises first and second transistors formed on the semiconductor substrate and first and second load devices formed on the semiconductor substrate; upper and lower word lines for selecting the memory cells; bit lines for reading and writing information of the memory cells; and coupling devices for electrically interconnecting the bit lines and the memory cells, wherein buried layers of the first and second transistors are isolated from the buried layers of the first and second load devices and/or from buried layers of the coupling devices, and wherein the first and second transistors employ the buried layers as emitters, respectively, wherein each memory cell is constructed by interconnecting a base of said first transistor and a collector of said second transistor and interconnecting a collector of said first transistor and a base of said second transistor, said load devices are first and second pnp transistors, a collector of said first pnp transistor is connected to a base of said first transistors and a collector of said second transistor, a collector of said second pnp transistor is connected to a base of said second transistor and a collector of said first transistor, and emitters of said first and second pnp transistors are electrically connected to said upper word line, wherein a base of the first pnp transistor is connected to a collector of the first transistor and the base of the second transistor, wherein a base of the second pnp transistor is connected to a collector of the second transistor and the base of the first transistor, and wherein emitters of said first and second transistors are electrically connected to the lower word line.
Claim 3
Dependent Claim
25 words
A semiconductor memory according to claim 1, wherein said pnp transistors have shielding means for shielding the pnp transistors from noise produced within said substrate.
Claim 4
Dependent Claim
26 words
A semiconductor memory according to claim 2, wherein said shielding means is a doped region and wherein a predetermined voltage is applied to said doped region.
Claim 5
Dependent Claim
38 words
A semiconductor memory according to claim 1, further comprising: a first insulation region provided between the first transistor and the first load device, and a second insulation region provided between the second transistor and the second load device.
Claim 6
Dependent Claim
35 words
A semiconductor memory according to claim 1, wherein a first insulator region is provided so as to surround the first transistor, and a second insulator region is provided so as to surround the second transistor.
Claim 7
Dependent Claim
35 words
A semiconductor memory according to claim 1, wherein the first transistor, the second transistor, the first load device, the second load device, and the coupling devices are isolated by an insulation region from each other.
Claim 8
Dependent Claim
200 words
A semiconductor memory comprising: a semiconductor substrate; bipolar transistor formed on the semiconductor substrate; a memory cell array comprising a plurality of memory cell circuits arranged along word lines or bit lines, said memory cell circuit including at least two cross-coupled transistors of a first type isolated from each other; each of said first type transistors having a first layer of a first conductivity type buried in said semiconductor substrate and serving as an emitter, a second layer formed over the first type conductivity doped layer and serving as a base and a third layer formed over the second layer; a first and second collector load device for said memory cell circuit each including a transistor of a second type which is different from said first type; the bases of said first type and the collector of said second type transistors being interconnected to construct a pnpn structure; a fourth layer of the same conductivity type as that of the emitter of said first type transistor being formed below said second type transistor; and said fourth layer being connected to the word line, the bit line, a signal line like the word or bit line or a power supply line.
Claim 9
Dependent Claim
200 words
A semiconductor memory comprising: a semiconductor substrate; bipolar transistor formed on the semiconductor substrate; a memory cell array comprising a plurality of memory cell circuits arranged along word lines or bit lines, said memory cell circuit including at least two cross-coupled transistors of a first type isolated from each other; each of said first type transistors having a first layer of a first conductivity type buried in said semiconductor substrate and serving as an emitter, a second layer formed over the first type conductivity doped layer and serving as a base and a third layer formed over the second layer; a first and second collector load device for said memory cell circuit each including a transistor of a second type which is different from said first type; the bases of said first type and the collector of said second type transistors being interconnected to construct a pnpn structure; a fourth layer of the same conductivity type as that of the emitter of said first type transistor being formed below said second type transistor; and said fourth layer being connected to the word line, the bit line, a signal line like the word or bit line or a power supply line.
Claim 10
Dependent Claim
36 words
A semiconductor memory according to claim 7, wherein the base contact of each of said transistors is formed on a side surface of said second layer of a second conductivity type formed in a protruding region.
Claim 11
Dependent Claim
38 words
A semiconductor memory according to claim 7, further comprising: a first insulation region provided between the first transistor and the first load device, and a second insulation region provided between the second transistor and the second load device.
Claim 12
Dependent Claim
42 words
A semiconductor memory according to claim 7, wherein a first insulator region is provided so as to surround one of the two cross-coupled transistors, and a second insulator region is provided so as to surround the other of the two cross-coupled transistors.
Claim 13
Dependent Claim
126 words
A semiconductor memory comprising: a semiconductor substrate; memory cells, each of which comprises first and second transistors formed on the semiconductor substrate, and first and second load devices formed on the semiconductor substrate; word lines for selecting the memory cells; bit lines for reading and writing information of the memory cells; and coupling devices for electrically interconnecting the bit lines and the memory cells, wherein the first and second transistors employ buried layers within the substrate as emitters, respectively, and wherein the first and second load devices are isolated from the substrate, and further wherein at least one of the first and second load devices include a shield layer not forwardly biased with a buried layer of either one of the first and second load devices.
Claim 14
Dependent Claim
126 words
A semiconductor memory comprising: a semiconductor substrate; memory cells, each of which comprises first and second transistors formed on the semiconductor substrate, and first and second load devices formed on the semiconductor substrate; word lines for selecting the memory cells; bit lines for reading and writing information of the memory cells; and coupling devices for electrically interconnecting the bit lines and the memory cells, wherein the first and second transistors employ buried layers within the substrate as emitters, respectively, and wherein the first and second load devices are isolated from the substrate, and further wherein at least one of the first and second load devices include a shield layer not forwardly biased with a buried layer of either one of the first and second load devices.
Claim 15
Dependent Claim
33 words
A semiconductor memory according to claim 11, wherein the buried layers of the first and second transistors are isolated from the buried layers of either one of the first and second load devices.
Claim 16
Dependent Claim
13 words
A semiconductor memory according to claim 11, wherein the coupling devices are diodes.
Claim 17
Dependent Claim
117 words
A semiconductor memory according to claim 11, wherein said memory cell is constructed by interconnecting the base of said first transistor and the collector of said second transistor and interconnecting the collector of said first transistor and the base of said second transistor, said load devices are first and second pnp transistors, the collector of said first pnp transistor is connected to the base of said first transistor and the collector of said second transistor, the collector of said second pnp transistor is connected to the base of said second transistor and the collector of said first transistor, and the emitters of said first and second pnp transistors are electrically connected to one of said word lines.
Claim 18
Dependent Claim
38 words
A semiconductor memory according to claim 22, further comprising: a first insulation region provided between the first transistor and the first load device, and a second insulation region provided between the second transistor and the second load device.
Claim 19
Dependent Claim
35 words
A semiconductor memory according to claim 11, wherein a first insulator region is provided so as to surround the first transistor, and a second insulator region is provided so as to surround the second transistor.
Claim 20
Dependent Claim
35 words
A semiconductor memory according to claim 11, wherein the first transistor, the second transistor, the first load device, the second load device and the coupling devices are isolated by an insulation region from each other.
Claim 21
Dependent Claim
232 words
A semiconductor memory comprising: a semiconductor substrate; memory cells, each of comprises first and second transistors formed on the semiconductor substrate, wherein the first and second transistors have a first protruding portion, said first protruding portion having a single crystal side surface; an insulation film having a first opening, said insulation film being formed on a surface of said substrate so as to provide said first opening is located at said first protruding portion; a first conductive layer formed on said single crystal surface of the first protruding portion and on said insulation film, wherein said first conductive layer is formed by being deposited on an exposed surface of said first protruding portion after said first protruding portion has been formed; a first region formed in said first protruding portion in contact with said first conductive layer; first and second load devices formed on the semiconductor substrate; word lines for selecting the memory cells; bit lines for reading and writing information of the cells; and coupling devices for electrically interconnecting the bit lines and the memory cells, wherein buried layers of the first and second transistors are isolated from buried layers of the coupling devices, and wherein the first and second transistors employ the buried layers as emitters, respectively, and further wherein the coupling devices are transistors having a buried layer isolated from the buried layer of the first and second transistors.
Claim 22
Dependent Claim
232 words
A semiconductor memory comprising: a semiconductor substrate; memory cells, each of comprises first and second transistors formed on the semiconductor substrate, wherein the first and second transistors have a first protruding portion, said first protruding portion having a single crystal side surface; an insulation film having a first opening, said insulation film being formed on a surface of said substrate so as to provide said first opening is located at said first protruding portion; a first conductive layer formed on said single crystal surface of the first protruding portion and on said insulation film, wherein said first conductive layer is formed by being deposited on an exposed surface of said first protruding portion after said first protruding portion has been formed; a first region formed in said first protruding portion in contact with said first conductive layer; first and second load devices formed on the semiconductor substrate; word lines for selecting the memory cells; bit lines for reading and writing information of the cells; and coupling devices for electrically interconnecting the bit lines and the memory cells, wherein buried layers of the first and second transistors are isolated from buried layers of the coupling devices, and wherein the first and second transistors employ the buried layers as emitters, respectively, and further wherein the coupling devices are transistors having a buried layer isolated from the buried layer of the first and second transistors.
Claim 23
Dependent Claim
35 words
A semiconductor memory according to claim 13, wherein the first transistor, the second transistor, the first load device, the second load device and the coupling devices are isolated by an insulation region from each other.
Claim 24
Dependent Claim
69 words
A semiconductor memory according to claim 18, wherein each memory cell is constructed by interconnecting a base of said first transistor and a collector of the second transistor and interconnecting a collector of said first transistor and a base of said second transistor, and wherein said load devices are Schottky barrier diodes electrically connected to nodes where the collectors and bases of said first and second transistors are connected.
Claim 25
Dependent Claim
28 words
A semiconductor memory according to claim 20, wherein said Schottky barrier diodes include shielding means for shielding the Schottky barrier diodes from noise produced within the semiconductor substrate.
Claim 26
Dependent Claim
38 words
A semiconductor memory according to claim 21, wherein said shielding means is a doped region of a same conduction type as a conductivity type of said semiconductor substrate, and wherein a voltage is applied to said doped region.
Claim 27
Dependent Claim
20 words
A semiconductor memory according to claim 18, wherein the first and second load devices are isolated from the semiconductor substrate.
Claim 28
Dependent Claim
19 words
A semiconductor memory according to claim 23, wherein the first and second load devices are formed on an insulator.
Claim 29
Dependent Claim
29 words
A semiconductor memory according to claim 18, wherein the buried layers of the first and second transistors are isolated from buried layers of the first and second load devices.
Claim 30
Dependent Claim
14 words
A semiconductor memory according to claim 18, wherein said load devices are pnp transistors.
Claim 31
Dependent Claim
25 words
A semiconductor memory according to claim 26, wherein said pnp transistor have shielding means for shielding the pnp transistors from noise produced within said substrate.
Claim 32
Dependent Claim
26 words
A semiconductor memory according to claim 27, wherein said shielding means is a doped region, and wherein a predetermined voltage is applied to said doped region.
Claim 33
Dependent Claim
220 words
A semiconductor memory comprising: a semiconductor substrate; a plurality of memory cells, each of which comprises first and second transistors formed on the semiconductor substrate and first and second load devices formed on the semiconductor substrate; upper and lower word lines for selecting the memory cells; bit lines for reading and writing information of the cells; and third and fourth transistors for electrically interconnecting the bit lines and the memory cell, wherein buried layers of the first and second transistors are isolated from buried layers of the third and fourth transistors, wherein the first, second, third and fourth transistors employ buried layers as emitters respectively, and further wherein emitters of the first and second transistors are electrically connected to the lower word line, wherein emitters of the third and fourth transistors are electrically connected to the bit lines, and bases of the third and fourth transistors are electrically connected to bases of the first and second transistors, respectively, and collectors of the third and fourth transistors are electrically connected to collectors of the first and second transistors, respectively, wherein the first load devices are electrically coupled between the collectors of first and third transistors and the upper word line, and wherein the second load devices are provided between the collector of second and fourth transistors and the upper word line.
Claim 34
Dependent Claim
220 words
A semiconductor memory comprising: a semiconductor substrate; a plurality of memory cells, each of which comprises first and second transistors formed on the semiconductor substrate and first and second load devices formed on the semiconductor substrate; upper and lower word lines for selecting the memory cells; bit lines for reading and writing information of the cells; and third and fourth transistors for electrically interconnecting the bit lines and the memory cell, wherein buried layers of the first and second transistors are isolated from buried layers of the third and fourth transistors, wherein the first, second, third and fourth transistors employ buried layers as emitters respectively, and further wherein emitters of the first and second transistors are electrically connected to the lower word line, wherein emitters of the third and fourth transistors are electrically connected to the bit lines, and bases of the third and fourth transistors are electrically connected to bases of the first and second transistors, respectively, and collectors of the third and fourth transistors are electrically connected to collectors of the first and second transistors, respectively, wherein the first load devices are electrically coupled between the collectors of first and third transistors and the upper word line, and wherein the second load devices are provided between the collector of second and fourth transistors and the upper word line.
Claim 35
Dependent Claim
20 words
A semiconductor memory according to claim 27, wherein the first and second load devices are isolated from the semiconductor substrate.
Claim 36
Dependent Claim
38 words
A semiconductor memory according to claim 29, further comprising: a first insulation region provided between the first transistor and the first load device, and a second insulation region provided between the second transistor and the second load device.
Claim 37
Dependent Claim
35 words
A semiconductor memory according to claim 29, wherein a first insulator region is provided so as to surround the first transistor, and a second insulator region is provided so as to surround the second transistor.
Claim 38
Dependent Claim
38 words
A semiconductor memory according to claim 29, wherein the first transistor, the second transistor, the first load device, the second load device, the third transistor and the fourth transistor are isolated by an insulation region from each other.
Claim 39
Dependent Claim
69 words
A semiconductor memory according to claim 29, wherein each memory cell is constructed by interconnecting a base of said first transistor and a collector of the second transistor and interconnecting a collector of said first transistor and a base of said second transistor, and wherein said load devices are Schottky barrier diodes electrically connected to nodes where the collectors and bases of said first and second transistors are connected.
Claim 40
Dependent Claim
28 words
A semiconductor memory according to claim 34, wherein said Schottky barrier diodes have shielding means for shielding the Schottky barrier diodes from noise produced within the semiconductor substrate.
Claim 41
Dependent Claim
39 words
A semiconductor memory according to claim 35, wherein said shielding means is a doped region of a same conduction type as a conductivity type of said semiconductor substrate, and wherein a predetermined voltage is applied to said doped region.
Claim 42
Dependent Claim
19 words
A semiconductor memory according to claim 29, wherein the first and second load devices are formed on an insulator.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-09-10 | 1994-03-12 | 1994-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-10 | 1998-03-12 | 1998-09-11 | $3760.00 | Window Closed / Lapsed |
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