Ternary logic circuit using resonant-tunneling transistors

Claim 2

A logic circuit operatively connected to receive a pulse signal, comprising: at least three resonant-tunneling transistors connected in series to form a closed loop, each said resonant-tunneling transistor having an emitter, a base, a superlattice formed between the emitter and the base and having a quantum well having at least one resonant energy level, and a collector, and having a negative resistance characteristic of a negative transfer conductance, each resonant-tunneling transistor conducting a current between the collector and the emitter, the current having one of at least three different current values including a first, a second or a third value, defined by said negative resistance characteristic and in response to a base voltage having one of three different voltage values including a first, a second or a third value, said third current value being between said first and second current values, and said second voltage value being between said first and third voltage values, said logic circuit holding at least three states, each state being, respectively, a high value, a low value, and a value approximately between said high and low values of said three resonant-tunneling transistors in response to the pulse signal applied to the base of one of said three resonant-tunneling transistors, the pulse signals having an amplitude of one of said first to third voltage values.

Claim 3

A logic circuit according to claim 1, wherein said second voltage value applied to the base is approximately 2·E X /q, wherein E X is an energy level of a sub-band at a quantum well in a superlattice in said resonant-tunneling transistor, and wherein q represents a charge on carriers in said resonant-tunneling transistor, said first voltage being lower than 2·E X /q and said third voltage being higher than 2·E X /q.

Claim 4

A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines intersecting said word lines; and a plurality of memory cells connected at the intersection of said word lines and bit lines in a matrix fashion, each one of said plurality of memory cells including three series connected gate circuits forming a closed loop; and transfer gates, operatively connected to said three series connected gate circuits and operatively connected to said word lines and said bit lines, each of said gate circuits including: resonant-tunneling transistors having an emitter, base, a superlattice formed between the emitter and base and having a quantum well having at least one resonant energy level, and collector, and having a negative resistance characteristic of a negative transfer conductance; and a resistor operatively connected in series with said resonant-tunneling transistors, each of said resonant-tunneling transistors conducting a current between the collector and emitter, said current having one of at least three different current values including first, second, and third values defined by said negative resistance characteristic and in response to a base voltage having one of three different voltage values including first, second and third values, a third current value being between the first and second current values, and a second voltage value being between the first and third voltage values, each one of said memory cells holding at least three states, a high state, a low state, and a state approximately between said high and low states, in response to a signal applied between said bit lines and word lines, said signal having an amplitude corresponding to one of said first to third voltage values.

Claim 5

A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines intersecting said word lines; and a plurality of memory cells connected at the intersection of said word lines and bit lines in a matrix fashion, each one of said plurality of memory cells including three series connected gate circuits forming a closed loop; and transfer gates, operatively connected to said three series connected gate circuits and operatively connected to said word lines and said bit lines, each of said gate circuits including: resonant-tunneling transistors having an emitter, base, a superlattice formed between the emitter and base and having a quantum well having at least one resonant energy level, and collector, and having a negative resistance characteristic of a negative transfer conductance; and a resistor operatively connected in series with said resonant-tunneling transistors, each of said resonant-tunneling transistors conducting a current between the collector and emitter, said current having one of at least three different current values including first, second, and third values defined by said negative resistance characteristic and in response to a base voltage having one of three different voltage values including first, second and third values, a third current value being between the first and second current values, and a second voltage value being between the first and third voltage values, each one of said memory cells holding at least three states, a high state, a low state, and a state approximately between said high and low states, in response to a signal applied between said bit lines and word lines, said signal having an amplitude corresponding to one of said first to third voltage values.

Claim 6

A semiconductor memory device according to claim 3, wherein said second voltage value applied to the base of said resonant-tunneling transistor is equal to approximately 2·E X /q, wherein E X is an energy level of a sub-band at a quantum well in a superlattice in said resonant-tunneling transistor, wherein q represents a charge on carriers in said resonant-tunneling transistor, said first voltage being lower than 2·E X /q and said third voltage being higher than 2·E X /q.

Claim 7

A semiconductor memory device according to claim 4, further comprising a plurality of sense amplifiers, each including three series-connected gate circuits operatively connectable to said bit lines for receiving data from said memory cells, each one of said gate circuits including: a resonant-tunneling transistor; and a resistor operatively connected in series with said resonant-tunneling transistor.

Claim 8

A semiconductor memory device according to claim 5, further comprising a plurality of write amplifiers, each amplifier including three series connected gate circuits, operatively connectable to said bit lines, for outputting data to be stored in said memory cells, each of said gate circuits including: a resonant-tunneling transistor; and a resistor operatively connected in series with said resonant tunneling transistor.

Claim 9

A logic gate according to claim 2, wherein said resonant-tunneling transistor comprises a resonant-tunneling hot electron transistor (RHET).

Claim 10

A logic gate circuit according to claim 2, wherein said resonant-tunneling transistor comprises a resonant-tunneling bi-polar transistor (RBT).

Claim 11

A logic gate circuit according to claim 6, wherein said resonant-tunneling transistor comprises a resonant-tunneling hot electron transistor (RHET).

Claim 12

A logic gate circuit according to claim 6, wherein said resonant-tunneling transistor comprises a resonant-tunneling bi-polar transistor (RBT).

Claim 13

A logic gate operatively connected to receive a signal, comprising: a resonant-tunneling transistor having a base, an emitter, a collector, and a superlattice layer formed between the base and the emitter, the superlattice layer including at least one quantum well layer formed between first and second barrier layers, said quantum well layer having at least one resonant energy level, said resonant-tunneling transistor receiving an input signal at the base from said logic gate, said input signal being within one of three voltage ranges, a first voltage range, a second voltage range and a third voltage range, and conducting a current between the collector and the emitter through the superlattice layer, the value of the current depending on the voltage value of said input signal, and the characteristic of the current with respect to the input voltage value exhibiting a minimum current value, a first positive resistance characteristic between said minimum current value and said local maximum current value, a negative resistance characteristic between said local maximum current value and said local minimum current value, and a second positive resistance characteristic above said local minimum current value, the input voltage providing said minimum current value being in said first voltage range, the input voltage providing said local maximum current value being in said second voltage range, and the input voltage providing said local minimum current value being in said third voltage range; and a resistor operatively connected in series with said resonant-tunneling transistor, said logic gate outputting a terminal voltage of said resistor as an output signal having an output voltage within one of a first output voltage range, a second output voltage range and a third output voltage range, which respectively correspond to said first, third and second input voltage ranges, the potential height of at least one of said first and second barrier layers being arranged so that said first, second and third output voltage ranges are separate from each other.

Claim 14

A logic gate operatively connected to receive a signal, comprising: a resonant-tunneling transistor having a base, an emitter, a collector, and a superlattice layer formed between the base and the emitter, the superlattice layer including at least one quantum well layer formed between first and second barrier layers, said quantum well layer having at least one resonant energy level, said resonant-tunneling transistor receiving an input signal at the base from said logic gate, said input signal being within one of three voltage ranges, a first voltage range, a second voltage range and a third voltage range, and conducting a current between the collector and the emitter through the superlattice layer, the value of the current depending on the voltage value of said input signal, and the characteristic of the current with respect to the input voltage value exhibiting a minimum current value, a first positive resistance characteristic between said minimum current value and said local maximum current value, a negative resistance characteristic between said local maximum current value and said local minimum current value, and a second positive resistance characteristic above said local minimum current value, the input voltage providing said minimum current value being in said first voltage range, the input voltage providing said local maximum current value being in said second voltage range, and the input voltage providing said local minimum current value being in said third voltage range; and a resistor operatively connected in series with said resonant-tunneling transistor, said logic gate outputting a terminal voltage of said resistor as an output signal having an output voltage within one of a first output voltage range, a second output voltage range and a third output voltage range, which respectively correspond to said first, third and second input voltage ranges, the potential height of at least one of said first and second barrier layers being arranged so that said first, second and third output voltage ranges are separate from each other.

Claim 15

A logic gate according to claim 11, wherein said potential height of at least one of said first and second barrier layers being arranged so that said local maximum current value is approximately twice said local minimum current value, and said minimum current value is approximately zero.

Claim 16

A logic gate according to claim 11, wherein said input voltage value having the local maximum current value is equal to approximately 2·E X /q, wherein E X is an energy level of a sub-band at a quantum well in the superlattice in said resonant-tunneling transistor, and wherein q represents charges on carriers in said resonant-tunneling transistor, said first input voltage range being lower than 2·E X /q and said third input voltage range being higher than 2·E X /q.

Claim 17

A logic gate circuit according to claim 11, wherein said resonant-tunneling transistor comprises a resonant-tunneling hot electron transistor (RHET).

Claim 18

A logic gate circuit according to claim 11, wherein said resonant-tunneling transistor comprises a resonant-tunneling bi-polar transistor (RBT).