Liquid crystal display device and method of driving the same

Claim 1

A liquid crystal display panel comprising: a first substrate; a second substrate having a transparent conductive film thereon; a liquid crystal layer sandwiched between the first and the second substrates; a plurality of pixel electrodes formed on the first substrate and associated with respective intersections of parallel rows and parallel columns wherein the rows comprise a plurality of gate lines and the columns comprise a plurality of data lines; a plurality of thin film transistors formed on the first substrate for driving the pixel electrodes, respectively, each transistor having a gate connected to an associated gate line and two electrodes one of which is connected to one of the plurality of pixel electrodes and another electrode is connected to an associated data line; the plurality of gate lines being driven successively in a predetermined order for on-off control of the thin film transistors, each of the pixel electrodes in each one row being made to overlap the gate line in another row adjacent to the one row so as to provide capacitive coupling between the overlapping pixel electrode and the gate line; wherein the capacitive coupling between the overlapping pixel electrode and the gate line is represented by a capacitance C add which satisfies the following formula: C.sub.add =(V.sub.1 /V.sub.2)Cgs where Cgs indicates a parasitic gate-source capacitance of the thin film transistor; means for applying a driving voltage to each one of the plurality of gate lines, the driving voltage having a waveform which is at a voltage level V ON when the thin film transistors connected to said one gate line are to be ON-state, at a voltage level V OFF when said thin film transistors are to be OFF-state, and a voltage level V COMP just before said driving voltage goes up to the voltage level V ON and when the driving voltage applied to the precedingly driven gate line is at the voltage level V ON , where V ON >V OFF >V COMP .

Claim 9

A method of driving a liquid crystal display panel comprising a first substrate; a second substrate having a transparent conductive film thereon; a liquid crystal layer sandwiched between the first and the second substrates; a plurality of pixel electrodes formed on the first substrate and associated with respective intersections of first to n-th parallel rows and parallel columns, where n is an integer, and wherein the rows comprise a plurality of gate lines and the columns comprise a plurality of data lines; a plurality of thin film transistors formed on the first substrate for driving the pixel electrodes, respectively, each transistor having a gate and two electrodes one of which is connected to the associated pixel electrode; and an other electrode is connected to an associated data line; wherein the plurality of gate lines include a plurality of first to n-th gate lines formed on the first substrate corresponding to the first to the n-th rows, respectively, each gate line, generally represented by (i-th) gate line where i is an integer satisfying 1≦i≦n, being connected to the gates of the thin film transistors associated with the pixel electrodes disposed in the i-th row and the gate lines being driven successively in an order of the first to the n-th gate line for on-off control of the thin film transistors of which the gates are connected to the gate line as driven; each of the pixel electrodes disposed in the i-th row overlapping with the (i+1)-th gate line so as to provide capacitive coupling between the overlapping pixel electrode and the gate line, wherein said capacitive coupling between the overlapping pixel electrode and the gate line is represented by a capacitance C add which satisfies the following formula: C.sub.add =(V.sub.1 /V.sub.2)·C.sub.gs where C gs indicates a parasitic gate-source capacitance of the thin film transistor, said method comprising the steps of: applying to the i-th gate line a first driving voltage which varies a voltage value v 1 at an off time for turning off the thin film transistors whose gates are connected to the i-th gate line; and applying to the (i+1)-th gate line a second driving voltage having a wave form which varies, at a time corresponding to the off time for the gate voltage applied to the i-th gate line a voltage value (v 1 +v 2 ) in a direction opposite to that of the voltage v 1 , where v 1 >0 and v 2 >0.

Claim 10

A method of driving a liquid crystal display panel comprising a first substrate; a second substrate having a transparent conductive film thereon; a liquid crystal layer sandwiched between the first and the second substrates; a plurality of pixel electrodes formed on the first substrate and associated with respective intersections of first to n-th parallel rows and parallel columns, where n is an integer, and wherein the rows comprise a plurality of gate lines and the columns comprise a plurality of data lines; a plurality of thin film transistors formed on the first substrate for driving the pixel electrodes, respectively, each transistor having a gate and two electrodes one of which is connected to the associated pixel electrode; and an other electrode is connected to an associated data line; wherein the plurality of gate lines include a plurality of first to n-th gate lines formed on the first substrate corresponding to the first to the n-th rows, respectively, each gate line, generally represented by (i-th) gate line where i is an integer satisfying 1≦i≦n, being connected to the gates of the thin film transistors associated with the pixel electrodes disposed in the i-th row and the gate lines being driven successively in an order of the first to the n-th gate line for on-off control of the thin film transistors of which the gates are connected to the gate line as driven; each of the pixel electrodes disposed in the i-th row overlapping with the (i+1)-th gate line so as to provide capacitive coupling between the overlapping pixel electrode and the gate line, wherein said capacitive coupling between the overlapping pixel electrode and the gate line is represented by a capacitance C add which satisfies the following formula: C.sub.add =(V.sub.1 /V.sub.2)·C.sub.gs where C gs indicates a parasitic gate-source capacitance of the thin film transistor, said method comprising the steps of: applying to the i-th gate line a first driving voltage which varies a voltage value v 1 at an off time for turning off the thin film transistors whose gates are connected to the i-th gate line; and applying to the (i+1)-th gate line a second driving voltage having a wave form which varies, at a time corresponding to the off time for the gate voltage applied to the i-th gate line a voltage value (v 1 +v 2 ) in a direction opposite to that of the voltage v 1 , where v 1 >0 and v 2 >0.