Branching control system for microcomputer

Abstract

Abstract PURPOSE:To branch with the small number of states and to call a sub-routine by dividing a branching destination address to a low-order part and a high-order part and holding, replacing the branching destination address by a branching destination address read from a branching destination address table to output it. CONSTITUTION:First and second branching destination address tables 11, 12 for holding the low-order part and the high-order part of the branching destination address to respective addresses corresponding to a condition value for designating a branching destination and a CPU 1 for setting the condition value for designating this branching destination to the address register 13 of the branching destination address table, and then, starting to read a branching instruction read from a program memory are provided and the low-order part and the high-order part of the branching destination address read from the first and the second branching destination address tables 11, 12 subsequently to the instruction code of the branching instruction read from the program memory are outputted on a data bus 8. Thereby, a processing time for branching or calling the sub-routine can be remarkably shortened and the processing capability of a microcomputer is remarkably improved.

Inventors

• 👤 Noriyuki Takagi

Bibliographic Details