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US4954988A
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Memory device wherein a shadow register corresponds to each memory cell
Assignee: Boeing North American Inc
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Filing: 1988-10-28
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Granted: 1990-09-04
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Expires: 2008-10-28
Abstract
Abstract A data storage device includes two registers associated with each cell of the memory. The first register forms a read/write memory register, and the second register forms a write-only shadow register connected to the memory register. During normal operations, each memory register operates as an independent random access memory (RAM) cell and each shadow register operates as an independent write-only RAM cell. When data is written to a shadow register, a flag bit is set. Subsequently, a validity check may be performed to verify the data. If the data does not verify, a clear line may be used to clear the flag bits. If the data verifies, the data in each shadow register with a flag bit set can be loaded into its corresponding memory register in a gang loading operation. If a shadow register flag bit is not set, the data in its corresponding memory register is not changed during gang loading.
Inventors
- 👤 James R. Robb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:51
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/74; G11C11/00; G11C11/005; G11C7/00; G11C7/10; G11C7/1078; G11C7/1087; G11C7/1093
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
101 words
A data storage device for use with a data bus, comprising: a plurality of memory cells; a plurality of shadow registers, each of said shadow registers connected to a corresponding one of said memory cells; and a plurality of multiplexers connected between corresponding ones of said memory cells and shadow registers for gang loading data from said shadow registers into said corresponding memory cells, each of said multiplexers having a first channel connected to the data bus and a second channel connected to said corresponding shadow register, said second channel for loading data from said shadow register into said memory cell.
Claim 2
Dependent Claim
101 words
A data storage device for use with a data bus, comprising: a plurality of memory cells; a plurality of shadow registers, each of said shadow registers connected to a corresponding one of said memory cells; and a plurality of multiplexers connected between corresponding ones of said memory cells and shadow registers for gang loading data from said shadow registers into said corresponding memory cells, each of said multiplexers having a first channel connected to the data bus and a second channel connected to said corresponding shadow register, said second channel for loading data from said shadow register into said memory cell.
Claim 3
Dependent Claim
25 words
The data storage device of claim 1, further comprising a second plurality of shadow registers, said second shadow registers connected, respectively, to said corresponding multiplexer.
Claim 4
Dependent Claim
36 words
The data storage device of claim 2, wherein each of said multiplexers has a third channel connected to said corresponding second shadow register for loading data from said second shadow register into said corresponding memory cell.
Claim 5
Dependent Claim
26 words
The data storage device of claim 1, wherein each of said shadow registers includes a flag bit settable when data is entered into said shadow register.
Claim 6
Dependent Claim
19 words
The data storage device of claim 4, further comprising means for clearing said flag bit in said shadow register.
Claim 7
Dependent Claim
83 words
A random access memory (RAM), comprising: a plurality of read/write memory cells; a plurality of write-only shadow registers; a plurality of multiplexers, each of said multiplexers connected between a corresponding one of said memory cells and a corresponding one of said shadow registers; a flag bit in each of said shadow registers settable when data is entered into said shadow register; and means for gang loading data from each of said shadow registers having a flag bit set into said corresponding memory cells.
Claim 8
Dependent Claim
83 words
A random access memory (RAM), comprising: a plurality of read/write memory cells; a plurality of write-only shadow registers; a plurality of multiplexers, each of said multiplexers connected between a corresponding one of said memory cells and a corresponding one of said shadow registers; a flag bit in each of said shadow registers settable when data is entered into said shadow register; and means for gang loading data from each of said shadow registers having a flag bit set into said corresponding memory cells.
Claim 9
Dependent Claim
19 words
The RAM of claim 6, further comprising means for clearing said flag bit in each of said shadow registers.
Claim 10
Dependent Claim
44 words
The RAM of claim 6, wherein each of said multiplexers comprises a first channel connected to a data bus and a second channel connected to said corresponding shadow register, said second channel for loading data from said shadow register into said corresponding memory cell.
Claim 11
Dependent Claim
24 words
The RAM of claim 8, further comprising a second plurality of shadow registers, each of said second shadow registers connected to said corresponding multiplexers.
Claim 12
Dependent Claim
35 words
The RAM of claim 9, wherein each of said multiplexers further comprises a third channel connected to said corresponding second shadow register for loading data from said second shadow register into said corresponding memory cell.
Claim 13
Dependent Claim
23 words
The RAM of claim 10, further comprising means for individually addressing each of said memory cells and said first and second shadow registers.
Claim 14
Independent Claim
79 words
A method of updating data in a data storage device having a plurality of memory cells, comprising the steps of: connecting each of the plurality of shadow registers to a corresponding one of the plurality of memory cells; entering data into selected ones of said shadow registers; setting a flag bit in each shadow register having entered data; and gang loading the data in each of said shadow registers having a flag bit set into the corresponding memory cells.
Claim 15
Independent Claim
79 words
A method of updating data in a data storage device having a plurality of memory cells, comprising the steps of: connecting each of the plurality of shadow registers to a corresponding one of the plurality of memory cells; entering data into selected ones of said shadow registers; setting a flag bit in each shadow register having entered data; and gang loading the data in each of said shadow registers having a flag bit set into the corresponding memory cells.
Claim 16
Dependent Claim
27 words
The method of claim 12, further comprising the step of verifying the data entered into said shadow registers before gand loading the data into the memory cells.
Claim 17
Dependent Claim
22 words
The method claim 13, further comprising the step of clearing said flag bits before gang loading if the data does not verify.
Claim 18
Dependent Claim
24 words
The method of claim 12, further comprising the step of clearing said flag bits after gang loading of the data into the memory cells.
References Cited (Backward Citations)
JPS607676A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-03 | 1994-03-05 | 1994-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-03 | 1998-03-05 | 1998-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-03 | 2002-03-05 | 2002-09-04 | $7700.00 | Window Closed / Lapsed |