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JPS607676A Expired / Lapsed JP ⏱️ 0.0 years remaining

Memory writing circuit

Assignee: Fujitsu Ltd
•
Filing: 1983-06-25
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Granted: —
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Expires: 2003-06-25
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Abstract

Abstract PURPOSE:To overlap or delete the contents of an input register to/from the contents of a memory simply by providing hard logic between the memory and the input register. CONSTITUTION:Signals are inputted from respective bits of an 8-bit input register in parallel to respective bits of the memory 10 through one input of each of 8 pieces of EOR circuits 12. A common function selecting signal ''0'' or ''1'' is applied to the other input of each of the EOR circuit 12. Respective bits of the input register 11 are branched and applied to one input of each of 8 pieces of multiplexers 13 and ''1'' is inputted to the other input of each of the multiplexers 13. The outputs of respective multiplexers 13 are inputted to one input of each of 8 pieces of AND circuits 14 and a write enable signal WE is inputted to the other input of each of the AND circuits 14. The outputs of the AND circuits 14 are inputted to respective bits of the memory 10. Thus, the contents of the input register can be simply overlapped or deleted to/from the contents of the memory.

Inventors

  • 👤 Kazuo Yokoyama
  • 👤 和夫 横山

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 01:03
CPC Classifications
G; G11; G11C; G11C7/00

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5449824U Cited

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