Display apparatus with image expanding capability

Claim 2

An image display apparatus of the type having a memory, a display, and a processor for sequentially feeding said display with image data read out of said memory in synchronism with a pixel synchronizing signal and scanning a screen of said display in synchronism with a horizontal and a vertical synchronizing signal to provide a picture image on said screen, wherein the improvement comprises: variable means for changing a frequency of said pixel synchronizing signal according to an instruction of said processor; address control means for storing a magnifying power signal from said processor and authorizing an output of said horizontal synchronizing signal once in a plurality of cycles; and means responsive to said authorized output to read out data from said memory and allotting said readout data to a plurality of pixel positions, thereby providing an expanded picture image, wherein said address control means comprises: a register for storing said magnifying power signal from said processor; an AND circuit for said horizontal and vertical synchronizing signals; a counter for counting the number of transitions in an output of said AND circuit; a comparator for comparing an output of said counter with an output of said register to generate a comparison signal; and an OR circuit for making a logical sum of said comparison signal and said vertical synchronizing signal to reset said counter so that said comparison signal is authorized to output once in a plurality of cycles of said horizontal synchronizing signal.

Claim 3

The image display apparatus of claim 1, wherein said counter performs counting by detecting a falling transition of said output from said AND circuit.

Claim 4

The image display apparatus of claim 1, wherein said counter performs counting by detecting a rising transition of said output from said AND circuit.

Claim 5

An image display apparatus of the type having a memory, a display, and a processor for sequentially feeding said display with image data read out of said memory in synchronism with a pixel synchronizing signal and scanning a screen of said display in synchronism with a horizontal and a vertical synchronizing signal to provide a picture image on said screen, wherein the improvement comprises: variable means for changing a frequency of said pixel synchronizing signal according to an instruction of said processor; address control means for storing a magnifying power signal from said processor and authorizing an output of said horizontal synchronizing signal once in a plurality of cycles; and means responsive to said authorized output to read out data from said memory and allotting said readout data to a plurality of pixel positions, thereby providing an expanded picture image, wherein said address control means comprises: a register for storing said magnifying power signal from said processor; an AND circuit for said horizontal and vertical synchronizing signals; a counter for counting the number of transitions in an output of said AND circuit; a comparator for comparing an output of said counter with an output of said register to generate a comparison signal; an OR circuit for making a logical sum of said comparison signal and said vertical synchronizing signal to reset said counter; and a selector responsive to said vertical synchronizing signal to select either said output of said register or a predetermined value preset and feeds it to said counter as an initial value so that said comparison signal is authorized for output once in a plurality of cycles of said horizontal synchronizing signal.

Claim 6

An image display apparatus of the type having a memory, a display, and a processor for sequentially feeding said display with image data read out of said memory in synchronism with a pixel synchronizing signal and scanning a screen of said display in synchronism with a horizontal and a vertical synchronizing signal to provide a picture image on said screen, wherein the improvement comprises: variable means for changing a frequency of said pixel synchronizing signal according to an instruction of said processor; address control means for storing a magnifying power signal from said processor and authorizing an output of said horizontal synchronizing signal once in a plurality of cycles; and means responsive to said authorized output to read out data from said memory and allotting said readout data to a plurality of pixel positions, thereby providing an expanded picture image, wherein said address control means comprises: a register for storing said magnifying power signal from said processor; an AND circuit for said horizontal and vertical synchronizing signals; a counter for counting the number of transitions in an output of said AND circuit; a comparator for comparing an output of said counter with an output of said register to generate a comparison signal; an OR circuit for making a logical sum of said comparison signal and said vertical synchronizing signal to reset said counter; and a selector responsive to said vertical synchronizing signal to select either said output of said register or a predetermined value preset and feeds it to said counter as an initial value so that said comparison signal is authorized for output once in a plurality of cycles of said horizontal synchronizing signal.

Claim 7

The image display apparatus of claim 4, wherein said counter performs counting by detecting a falling transition of said output from said AND circuit.

Claim 8

The image display apparatus of claim 4, wherein said counter performs counting by detecting a rising transition of said output from said AND circuit.

Claim 9

An image display apparatus of the type having a memory, a display, and a processor for sequentially feeding said display with image data read out of said memory in synchronism with a pixel synchronizing signal and scanning a screen of said display in synchronism with a horizontal and a vertical synchronizing signal to provide a picture image on said screen, wherein the improvement comprises: variable means for changing a frequency of said pixel synchronizing signal according to an instruction of said processor; address control means for storing said horizontal synchronizing signal, said vertical synchronizing signal, and a magnifying power signal from said processor and authorizing an output of said horizontal synchronizing signal once in a plurality of cycles; means responsive to said authorized output to read out data from said memory and allotting said readout data to a plurality of pixel positions, thereby providing an expanded picture image, wherein said variable means comprises: a second register for storing said magnifying power signal from said processor; a second counter having an initial value input terminal into which an initial value is applied, a clock input terminal into which said pixel synchronizing signal is applied, and an initialization request input terminal for counting said pixel synchronizing signal; a comparator for comparing an output of said counter with an output of said register to generate a comparison signal, which is fed back to said initialization request input terminal; and an AND circuit for receiving an output of said comparator and said pixel synchronizing signal and outputting a basic clock signal of a frequency which is lower than that of said pixel synchronizing signal.

Claim 10

An image display apparatus of the type having a memory, a display, and a processor for sequentially feeding said display with image data read out of said memory in synchronism with a pixel synchronizing signal and scanning a screen of said display in synchronism with a horizontal and a vertical synchronizing signal to provide a picture image on said screen, wherein the improvement comprises: variable means for changing a frequency of said pixel synchronizing signal according to an instruction of said processor; address control means for storing said horizontal synchronizing signal, said vertical synchronizing signal, and a magnifying power signal from said processor and authorizing an output of said horizontal synchronizing signal once in a plurality of cycles; means responsive to said authorized output to read out data from said memory and allotting said readout data to a plurality of pixel positions, thereby providing an expanded picture image, wherein said variable means comprises: a second register for storing said magnifying power signal from said processor; a second counter having an initial value input terminal into which an initial value is applied, a clock input terminal into which said pixel synchronizing signal is applied, and an initialization request input terminal for counting said pixel synchronizing signal; a comparator for comparing an output of said counter with an output of said register to generate a comparison signal, which is fed back to said initialization request input terminal; and an AND circuit for receiving an output of said comparator and said pixel synchronizing signal and outputting a basic clock signal of a frequency which is lower than that of said pixel synchronizing signal.