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US4952822A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated logic circuit with instability damping

Assignee: US Philips Corp
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Filing: 1988-11-10
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Granted: 1990-08-28
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Expires: 2008-11-10
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Abstract

Abstract In integrated logic circuits, at least one additional transistor may be provided in cascode connection with at least one other component in order to avoid detrimentally high electrical fields in components of such circuits. The control electrode is then connected to one of the power supply lines. When the state of the logic circuit changes, switching currents generate voltage peaks on the power supply lines due to the inductance of these lines. Via the chip capacitance these voltage peaks jump from one power supply line to the other. Thus, a positive feedback loop is formed which comprises one power supply line, the chip capacitance, the other power supply line and the additional transistor. Instabilities in such circuits are damped by inserting a resistance element between the control electrode of the additional transistor and the power supply line coupled thereto.

Inventors

  • 👤 Jan Dikken

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 15:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/003; H03K19/00346; H03K19/00361

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 102 words
An integrated logical circuit, comprising a first subcircuit coupled between a first supply line and a circuit output, a second sub-circuit coupled between the circuit output and a second supply line, whereby at least between one of the subcircuits and the circuit output a current conduction path of an additional transistor is placed for reducing electrical fields in parts of the respective subcircuit, a control electrode of said additional transistor being coupled solely to the supply to which the other of the subcircuits is coupled, characterized in that said control electrode is coupled to said one supply line via a resistive element.
Claim 2
Dependent Claim 102 words
An integrated logical circuit, comprising a first subcircuit coupled between a first supply line and a circuit output, a second sub-circuit coupled between the circuit output and a second supply line, whereby at least between one of the subcircuits and the circuit output a current conduction path of an additional transistor is placed for reducing electrical fields in parts of the respective subcircuit, a control electrode of said additional transistor being coupled solely to the supply to which the other of the subcircuits is coupled, characterized in that said control electrode is coupled to said one supply line via a resistive element.
Claim 3
Dependent Claim 44 words
An integrated logic circuit as claimed in claim 1, characterized in that the resistive element comprises a current path of a further transistor, a control voltage of the further transistor being substantially equal to the difference between voltages on the respective power supply lines.

References Cited (Backward Citations)

US4209713A Cited
US4694199A Cited
US4704547A Cited
US4710726A Cited
US4736123A Cited
US4771189A Cited
US4791323A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-08-27 1994-02-26 1994-08-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-08-27 1998-02-26 1998-08-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-08-27 2002-02-26 2002-08-28 $7700.00 Window Closed / Lapsed

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