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US4951159A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital modulation technique

Assignee: A I T Corp
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Filing: 1989-10-10
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Granted: 1990-08-21
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Expires: 2009-10-10
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Abstract

Abstract A digital pulse with modulator is described for use with a Raster-scanning print engine in which a grey scale having a high number of levels, typically at least 63, is described. This modulator reduces the amount of information requiring processing in the input multiple bit image signal by simulating one of the least significant bits as a delay applied to modulate the output print engine signal pulse width. With suitable speed components, a grey scale of at least about 255 levels can be provided.

Inventors

  • 👤 Gary Van Beek

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 19:23
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40; H04N1/405; H04N1/4055; H04N1/4056

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 140 words
In a method for producing an output image signal to drive a raster print engine from an multiple bit image input signal by generating in a signal generator a pulse having a width corresponding to the input image signal, the improvement comprising processing the multiple bit image input signal in a digital pulse width modulator which functions to reduce the number of bits in the multiple bit image input signal by separating from the input image signal at least one of the least significant bits in the input image signal; processing the remaining bits in the input image signals to provide an output signal pulse corresponding to acceptable number of grey scale levels; and simulating one of the separated bits by a delay signal which modifies the output signal pulse width in response to the value of the separated bit.
Claim 2
Dependent Claim 140 words
In a method for producing an output image signal to drive a raster print engine from an multiple bit image input signal by generating in a signal generator a pulse having a width corresponding to the input image signal, the improvement comprising processing the multiple bit image input signal in a digital pulse width modulator which functions to reduce the number of bits in the multiple bit image input signal by separating from the input image signal at least one of the least significant bits in the input image signal; processing the remaining bits in the input image signals to provide an output signal pulse corresponding to acceptable number of grey scale levels; and simulating one of the separated bits by a delay signal which modifies the output signal pulse width in response to the value of the separated bit.
Claim 3
Dependent Claim 38 words
A method according to claim 1 in which the two least significant bits are separated, the most insignificant bit is discarded, and the value of the other separated bit is used to modify the output signal pulse width.
Claim 4
Dependent Claim 16 words
A method according to claim 1 in which the input image signal is an 8-bit signal.
Claim 5
Dependent Claim 133 words
A digital pulse width modulator which comprises in combination: (i) a means to receive a multiple bit input image signal from an image signal generating means; (ii) a means to separate from the input image signal at least one bit including the most insignificant bit; (iii) a signal generator means including a counter means controlling the width of the pulse generated by the signal generator in response to the value of the remainder of the input image signal after separation of at least one bit; (iv) a clock means controlling the counter means; and (v) a delay means which receives one of the separated bits from the input image signal and which extends the width of the pulse generated by the signal generator in response to the value of the second separated bit.
Claim 6
Dependent Claim 133 words
A digital pulse width modulator which comprises in combination: (i) a means to receive a multiple bit input image signal from an image signal generating means; (ii) a means to separate from the input image signal at least one bit including the most insignificant bit; (iii) a signal generator means including a counter means controlling the width of the pulse generated by the signal generator in response to the value of the remainder of the input image signal after separation of at least one bit; (iv) a clock means controlling the counter means; and (v) a delay means which receives one of the separated bits from the input image signal and which extends the width of the pulse generated by the signal generator in response to the value of the second separated bit.
Claim 7
Dependent Claim 159 words
A digital pulse width modulation which comprises in combination: (i) a means to receive a multiple bit input image signal from an image signal generating means; (ii) a means to separate and discard from the input image signal a first bit consisting of the most insignificant bit; (iii) a means to separate from the input image signal a second bit consisting of the least significant bit int the remaining signal; (iv) a signal generator means including a counter means controlling the width of the pulse generated by the signal generator in response to the value of the input image signal remainder of the input image signal, after separation of the two bits; (v) a clock means controlling the counter means; and (vi) a delay means which receives the first separated bit from the input image signal and which extends the length of the pulse generated by the signal generator in response to the value of the second separated bit.
Claim 8
Dependent Claim 159 words
A digital pulse width modulation which comprises in combination: (i) a means to receive a multiple bit input image signal from an image signal generating means; (ii) a means to separate and discard from the input image signal a first bit consisting of the most insignificant bit; (iii) a means to separate from the input image signal a second bit consisting of the least significant bit int the remaining signal; (iv) a signal generator means including a counter means controlling the width of the pulse generated by the signal generator in response to the value of the input image signal remainder of the input image signal, after separation of the two bits; (v) a clock means controlling the counter means; and (vi) a delay means which receives the first separated bit from the input image signal and which extends the length of the pulse generated by the signal generator in response to the value of the second separated bit.
Claim 9
Dependent Claim 18 words
A digital pulse width modulator according to claim 4 wherein the input image signal is an 8-bit signal.
Claim 10
Dependent Claim 18 words
A digital pulse width modulator according to claim 5 wherein the input image signal is an 8-bit signal.
Claim 11
Independent Claim 279 words
An apparatus for generating a printed image containing at least 63 grey scale levels comprising in combination: (a) an image input signal generating means which provides multiple bit input image signal comprising at least 8 bits and corresponding to an image to be printed; (b) means to separate at least one least significant bit from the input image signal; (c) a clock means substantially synchronized with a print engine pixel clock means; wherein the frequency of the clock means is a whole number multiple of the frequency of the pixel clock means having a value of 2 n , wherein n is the number of bits remaining in the image signal after at least one bit has been separated from it; (d) a signal generating means including a counter means actuated by the clock means and which controls the width of the signal generator output pulse in response to the value of the input image signal; (e) a delay means receiving one of the separated bits in the image input signal which lengthens the signal generator output pulse in response to the value of the received separated bit to provide a pulse width modulated signal; (f) means to apply the pulse width modulated signal to a Raster scanning point engine for generating a series of successive scan lines, to cause the print engine to generate each scan line as a succession of printed segments the size of each of which is determined by the pulse width of the pulse width modulated signal, thereby to provide a variable density printed image comprising a plurality of printed segments corresponding to an image including a grey scale having at least 64 levels.
Claim 12
Independent Claim 279 words
An apparatus for generating a printed image containing at least 63 grey scale levels comprising in combination: (a) an image input signal generating means which provides multiple bit input image signal comprising at least 8 bits and corresponding to an image to be printed; (b) means to separate at least one least significant bit from the input image signal; (c) a clock means substantially synchronized with a print engine pixel clock means; wherein the frequency of the clock means is a whole number multiple of the frequency of the pixel clock means having a value of 2 n , wherein n is the number of bits remaining in the image signal after at least one bit has been separated from it; (d) a signal generating means including a counter means actuated by the clock means and which controls the width of the signal generator output pulse in response to the value of the input image signal; (e) a delay means receiving one of the separated bits in the image input signal which lengthens the signal generator output pulse in response to the value of the received separated bit to provide a pulse width modulated signal; (f) means to apply the pulse width modulated signal to a Raster scanning point engine for generating a series of successive scan lines, to cause the print engine to generate each scan line as a succession of printed segments the size of each of which is determined by the pulse width of the pulse width modulated signal, thereby to provide a variable density printed image comprising a plurality of printed segments corresponding to an image including a grey scale having at least 64 levels.
Claim 13
Dependent Claim 16 words
An apparatus according to claim 8 wherein the multiple bit input image signal comprises 8 bits.
Claim 14
Dependent Claim 28 words
An apparatus according to claim 8 wherein the separation means separates one least significant bit from the input image signal which bit is received by the delay means.
Claim 15
Dependent Claim 33 words
An apparatus according to claim 8 wherein the separat me separates two least significant bits; the most insignificant bit is discarded; and the remaining least significant bit is received by the delay means.

References Cited (Backward Citations)

US4661859A Cited
US4533958A Cited
US4814877A Cited
US4698688A Cited
US4809082A Cited
US4802105A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-08-20 1994-02-19 1994-08-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-08-20 1998-02-19 1998-08-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-08-20 2002-02-19 2002-08-21 $7700.00 Window Closed / Lapsed

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