Method of transmitting serial data between facsimile equipment and interface performing the same

Claim 3

An interface ciruit arrangement for transforming binary encoded data being exchanged in form of a serial data stream between a transmitting and a receiving facsimile transceiever both having different horizontal resolutions, and circuit arrangement comprising: means for receiving the serial data stream generated by the transmitting facsimile transceiver while scanning an original document and for separating subsequent portions of the data stream each representing a scanning line into a respective sequence of first data words each composed of n bits; means for evaluating the bit pattern of each first data word by determining the number and type of subsequent bit changes thereof; means for deriving therefrom a coincident sequence of second data words each composed of m bits by reproducing substantially said bit pattern of each corresponding first data word while arbitrarily padding of an insignificant bit if the resolution of the receiving facsimile transceiver is higher and consequently n is lower than m and by arbitrarily dropping of an insignificant bit, respectively if the resolution of the transmitting transceiver is higher and consequently n is higher that m, whereby n:m corresponds to the ratio of the different horizontal resolutions; and means for forming a serial stream of transformed data from the sequence of said second data words and transmitting the same to the receiving facsimile transceiver.

Claim 4

An interface ciruit arrangement for transforming binary encoded data being exchanged in form of a serial data stream between a transmitting and a receiving facsimile transceiever both having different horizontal resolutions, and circuit arrangement comprising: means for receiving the serial data stream generated by the transmitting facsimile transceiver while scanning an original document and for separating subsequent portions of the data stream each representing a scanning line into a respective sequence of first data words each composed of n bits; means for evaluating the bit pattern of each first data word by determining the number and type of subsequent bit changes thereof; means for deriving therefrom a coincident sequence of second data words each composed of m bits by reproducing substantially said bit pattern of each corresponding first data word while arbitrarily padding of an insignificant bit if the resolution of the receiving facsimile transceiver is higher and consequently n is lower than m and by arbitrarily dropping of an insignificant bit, respectively if the resolution of the transmitting transceiver is higher and consequently n is higher that m, whereby n:m corresponds to the ratio of the different horizontal resolutions; and means for forming a serial stream of transformed data from the sequence of said second data words and transmitting the same to the receiving facsimile transceiver.

Claim 5

The interface circuit arrangement as recited in claim 2, wherein said receiving and separating means comprise a series to parallel converter having a serial input connected to receive said serial data stream and having n parallel outputs.

Claim 6

The interface circuit arrangement as recited in claim 3, wherein said receiving and separating means further comprise: means for generating a first clock pulse train having a first pulse frequency being substantially identical to the frequency of the received serial data stream, said first clock pulse generating means being connected to furnish input control pulses to said series to parallel converter; and means for generating a second clock pulse train having a second clock pulse frequency being equal to 1/nth of the first pulse frequency, said second clock pulse generating means being connected to said series to parallel converter for supplying output control pulses.

Claim 7

The interface circuit arrangement as recited in claim 4, wherein said evaluating means and said means for deriving a sequence of second data words commonly comprise a memory unit having n selective address inputs connected to receive first data words consecutively, a corresponding plurality of storage locations each storing a respective one of the second data words, and m data outputs.

Claim 8

The interface circuit arrangement as recited in claim 5, wherein the memory unit further includes an address enable input connected to receive said second clock pulse train.

Claim 9

The interface circuit arrangement as recited in claim 6, wherein said memory unit is a read only memory.

Claim 10

The interface circuit arrangement as recited in claim 4, wherein said means for forming a serial stream of transformed data comprise a parallel to series converter having m parallel inputs connected to receive consecutively said second data words, and having a serial output furnishing said transformed data stream.

Claim 11

The interface circuit arrangement as recited in claim 8, wherein said means for forming a serial data stream of transformed data further comprise means for generating a third clock pulse train having a third pulse frequency substantially identical to the frequency of the transformed data stream, said third clock pulse generating means being connected to furnish output control pulses to said parallel to series converter.

Claim 12

The interface circuit arrangement as recited in claim 9, wherein said means for forming a serial data stream of transformed data further comprise means for generating a fourth clock pulse train having a fourth clock pulse frequency being equal to 1/mth of the third clock pulse frequency, said fourth clock pulse generating means being connected to said parallel to series converter for supplying input control pulses.

Claim 13

The interface circuit arrangement as recited in claim 2, for cooperation with facsimile having a horizontal resolution of 1728 bits and 1400 bits, respectively per scanning line, wherein variable n has a value of 5 and variable m has a value of 4.