Patent US4951142A successfully refreshed from Google Patents.
US4951142A
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Method and apparatus for transmission of synchronization signals between microprocessors in video system
Assignee: Philips GmbH
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Filing: 1988-04-29
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Granted: 1990-08-21
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Expires: 2008-04-29
Abstract
Abstract In order to couple together vertical-frequency synchronization signals generated by a computer connected to an data transmission system, the synchronization signals are generated by counting the clock pulses. A reference signal is transmitted to the computer or processor; the reference has a frequency which is a whole-number fraction of the desired frequency. Upon receipt in the processor (16) of the reference signal, a counter (19) provided for counting of the clock pulses is preset.
Inventors
- 👤 Friedrich Glaab
- 👤 Uwe Ritter
- 👤 Rainer Sturm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:45
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/06; H04N5/067; H04N5/073
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
108 words
In a data processing system having a plurality of individual processors (16) each generating a respective vertical-frequency synchronization signal, and connected together over data transmission means (6), a method of rendering said synchronization signals coincident, comprising the steps of obtaining each synchronization signal by counting clock pulses of the respective processor (16); feeding to each said processor (16), via said data transmission means, a reference signal, said reference signal having a frequency which is a whole-number fraction of the desired frequency of the synchronization signal; and upon receipt in each said processor (16) of said reference signal, resetting a counter (19) provided for counting of said clock pulses.
Claim 2
Dependent Claim
108 words
In a data processing system having a plurality of individual processors (16) each generating a respective vertical-frequency synchronization signal, and connected together over data transmission means (6), a method of rendering said synchronization signals coincident, comprising the steps of obtaining each synchronization signal by counting clock pulses of the respective processor (16); feeding to each said processor (16), via said data transmission means, a reference signal, said reference signal having a frequency which is a whole-number fraction of the desired frequency of the synchronization signal; and upon receipt in each said processor (16) of said reference signal, resetting a counter (19) provided for counting of said clock pulses.
Claim 3
Dependent Claim
18 words
Method according to claim 1, wherein said reference signal is generated by frequency division of a vertical-frequency signal.
Claim 4
Dependent Claim
11 words
Method according to claim 1, wherein said whole-number fraction is 1/64.
Claim 5
Dependent Claim
108 words
Method of coupling together vertical-frequency synchronization signals generated by a processor (16) connected to a data transmission system, comprising the steps of obtaining synchronization signals by counting clock pulses of the processor (16); feeding to said processor (16), via said data transmission system, a reference signal, said reference signal having a frequency which is a whole-number fraction of the desired frequency of the synchronization signal; and upon receipt in said processor (16) of said reference signal, resetting a counter (19) provided for counting of said clock pulses, and wherein said feeding step includes transmitting said reference signal to a plurality of processors (12-16), each generating a synchronization signal.
Claim 6
Dependent Claim
108 words
Method of coupling together vertical-frequency synchronization signals generated by a processor (16) connected to a data transmission system, comprising the steps of obtaining synchronization signals by counting clock pulses of the processor (16); feeding to said processor (16), via said data transmission system, a reference signal, said reference signal having a frequency which is a whole-number fraction of the desired frequency of the synchronization signal; and upon receipt in said processor (16) of said reference signal, resetting a counter (19) provided for counting of said clock pulses, and wherein said feeding step includes transmitting said reference signal to a plurality of processors (12-16), each generating a synchronization signal.
Claim 7
Dependent Claim
18 words
Method according to claim 4, wherein said reference signal is generated by frequency division of a vertical-frequency signal.
Claim 8
Dependent Claim
11 words
Method according to claim 4, wherein said whole-number fraction is 1/64.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-20 | 1994-02-19 | 1994-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-20 | 1998-02-19 | 1998-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-20 | 2002-02-19 | 2002-08-21 | $7700.00 | Window Closed / Lapsed |