Dynamic PLA circuit with no "virtual grounds"

Claim 2

A dynamic programmable logic array circuit comprising: AND logic plane means (12) for receiving input logic signals and performing predetermined logic operations thereon and for generating first output signals on a plurality of product term lines; said AND logic plane means (12) being formed of a plurality of N-channel AND plane programming transistors (18a, 18b, . . . 18m), each of said AND plane programming transistors having its drain electrode connected to a respective one of said plurality of product term lines and its source electrode connected to a power supply ground potential (VSS), the gate electrodes of said AND plane programming transistors being connected to receive a respective one of said input logic signals; inter-plane buffer means (22) for receiving said first output signals and for generating second input logic signals on a plurality of OR input lines; OR logic plane means (14) for receiving said second input logic signals and for performing a second predetermined logic function thereon and for generating second output signals on a plurality of sum term lines; said OR logic plane means (14) being formed of a plurality of N-channel OR plane programming transistors (26a, 26b, . . . 26n), each of said OR plane programming transistors having its drain electrode connected to a respective one of said plurality of sum term lines and its source electrode connected to the power supply ground potential (VSS); and said buffer means (22) being formed of a plurality of N-channel inter-plane FETs (23a, 23b, . . . 23n), each of said plurality of interplane FETs having its gate electrode coupled to a respective one of said plurality of product term lines and its source electrode connected to a respective one of said plurality of OR input lines, the drain electrodes cf said plurality of inter-plane FETs being connected to receive an OR plane evaluation signal.

Claim 3

A dynamic programmable logic array circuit as claimed in claim 1, further comprising AND plane precharging means (30) for precharging said plurality of product term lines during a precharging phase of an AND phase evaluation signal.

Claim 4

A dynamic programmable logic array circuit as claimed in claim 2, wherein said AND plane precharging means (30) comprises a plurality of P-channel AND plane precharging transistors (32a, 32b, . . . 32m), each of said plurality of AND plane precharging transistors having its source electrode connected to a supply potential (VCC) and its drain electrode connected to a respective one of said plurality of product term lines, the gate electrodes of said plurality of AND plane precharging transistors being connected to receive said AND plane evaluation signal.

Claim 5

A dynamic programmable logic array circuit as claimed in claim 1, further comprising OR plane precharging means (36) for precharging said plurality of sum term lines during a precharging phase of said OR plane evaluation signal.

Claim 6

A dynamic programmable logic array circuit as claimed in claim 4, wherein said OR plane precharging means (34) comprises a plurality of P-channel OR plane precharging transistors (38a, 38b, . . . 38n), each of said plurality of OR plane precharging transistors having its source electrode connected to a supply potential (VCC) and its drain electrode connected to a respective one of said plurality of sum term lines, the gate electrodes of said plurality of OR plane precharging transistors being connected to receive said OR plane evaluation signal.

Claim 7

A dynamic programmable logic array circuit comprising: AND logic plane means (12) for receiving input logic signals and performing predetermined logic operations thereon and for generating first output signals on a plurality of product term lines; said AND logic plane means (12) being formed of a plurality of N-channel AND plane programming transistors (18a, 18b, . . . 18m), each of said AND plane programming transistors having its drain electrode connected to a respective one of said plurality of product term lines and its source electrode connected to a power supply ground potential (VSS), the gate electrodes of said AND plane programming transistors being connected to receive a respective one of said input logic signals; inter-plane buffer means (22) for receiving said first output signals and for generating second input logic signals on a plurality of OR input lines; OR logic plane means (14) for receiving said second input logic signals and for performing a second predetermined logic function thereon and for generating second output signals on a plurality of sum term lines; said OR logic plane means (14) being formed of a plurality of N-channel OR plane programming transistors 26a, 26b, . . . 26n), each of said OR plane programming transistors having its drain electrode connected to a respective one of said plurality of sum term lines and its source electrode connected to the power supply ground potential (VSS); said buffer means (22) being formed of a plurality of N-channel inter-plane FETs (23a, 23b, . . . 23n), each of said plurality of interplane FETs having its gate electrode coupled to a respective one of said plurality of product term lines and its source electrode connected to a respective one of said plurality of OR input lines, the drain electrodes of said plurality of inter-plane FETs being connected to receive an OR plane evaluation signal; AND plane precharging means (30) coupled to said AND logic plane means (12) for precharging said plurality of product term lines during a precharging phase of an AND plane evaluation signal; and OR plane precharging means (36) coupled to said OR logic plane means (14) for precharging said plurality of sum term lines during a precharging phase of said OR plane evaluation signal.

Claim 8

A dynamic programmable logic array circuit comprising: AND logic plane means (12) for receiving input logic signals and performing predetermined logic operations thereon and for generating first output signals on a plurality of product term lines; said AND logic plane means (12) being formed of a plurality of N-channel AND plane programming transistors (18a, 18b, . . . 18m), each of said AND plane programming transistors having its drain electrode connected to a respective one of said plurality of product term lines and its source electrode connected to a power supply ground potential (VSS), the gate electrodes of said AND plane programming transistors being connected to receive a respective one of said input logic signals; inter-plane buffer means (22) for receiving said first output signals and for generating second input logic signals on a plurality of OR input lines; OR logic plane means (14) for receiving said second input logic signals and for performing a second predetermined logic function thereon and for generating second output signals on a plurality of sum term lines; said OR logic plane means (14) being formed of a plurality of N-channel OR plane programming transistors 26a, 26b, . . . 26n), each of said OR plane programming transistors having its drain electrode connected to a respective one of said plurality of sum term lines and its source electrode connected to the power supply ground potential (VSS); said buffer means (22) being formed of a plurality of N-channel inter-plane FETs (23a, 23b, . . . 23n), each of said plurality of interplane FETs having its gate electrode coupled to a respective one of said plurality of product term lines and its source electrode connected to a respective one of said plurality of OR input lines, the drain electrodes of said plurality of inter-plane FETs being connected to receive an OR plane evaluation signal; AND plane precharging means (30) coupled to said AND logic plane means (12) for precharging said plurality of product term lines during a precharging phase of an AND plane evaluation signal; and OR plane precharging means (36) coupled to said OR logic plane means (14) for precharging said plurality of sum term lines during a precharging phase of said OR plane evaluation signal.

Claim 9

A dynamic programmable logic array circuit as claimed in claim 6, wherein said AND plane precharging means (30) comprises a plurality of P-channel AND plane precharging transistors (32a, 32b, . . . 32m), each of said plurality of AND plane precharging transistors having its source electrode connected to a supply potential (VCC) and its drain electrode connected to a respective one of said plurality of product term lines, the gate electrodes of said plurality of AND plane precharging transistors being connected to receive said AND plane evaluation signal.

Claim 10

A dynamic programmable logic array circuit as claimed in claim 7, wherein said OR plane precharging means (36) comprises a plurality of P-channel OR plane precharging transistors (38a, 38b, . . . 38n), each of said plurality of OR plane precharging transistors having its source electrode connected to the supply potential (VCC) and its drain electrode connected to a respective one of said plurality of sum term lines, the gate electrodes of said plurality of OR plane precharging transistors being connected to receive said OR plane evaluation signal.

Claim 11

A dynamic programmable logic array circuit comprising: AND logic plane means (12) for receiving input logic signals and performing predetermined logic operations thereon and for generating first output signals on a plurality of product term lines; inter-plane buffer means (22) for receiving said first output signals and for generating second input logic signals on a plurality of OR input lines; OR logic plane means (14) for receiving said second input logic signals and for performing a second predetermined logic function thereon and for generating second output signals on a plurality of sum term lines; and said buffer means (22) being formed of a plurality of N-channel inter-plane FETs (23a, 23b, . . . 23n), each of said plurality of interplane FETs having its gate electrode coupled to a respective one of said plurality of product term lines and its source electrode connected to a respective one of said plurality of OR input lines, the drain electrodes of said plurality of inter-plane FETs being connected to receive an OR plane evaluation signal.

Claim 12

A dynamic programmable logic array circuit comprising: AND logic plane means (12) for receiving input logic signals and performing predetermined logic operations thereon and for generating first output signals on a plurality of product term lines; inter-plane buffer means (22) for receiving said first output signals and for generating second input logic signals on a plurality of OR input lines; OR logic plane means (14) for receiving said second input logic signals and for performing a second predetermined logic function thereon and for generating second output signals on a plurality of sum term lines; and said buffer means (22) being formed of a plurality of N-channel inter-plane FETs (23a, 23b, . . . 23n), each of said plurality of interplane FETs having its gate electrode coupled to a respective one of said plurality of product term lines and its source electrode connected to a respective one of said plurality of OR input lines, the drain electrodes of said plurality of inter-plane FETs being connected to receive an OR plane evaluation signal.