US4661728A
Expired / Lapsed
US
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Programmable logic array circuit
Assignee: NEC Electronics Corp
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Filing: 1985-09-11
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Granted: 1987-04-28
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Expires: 2005-09-11
Abstract
Abstract A programmable logic array (PLA) circuit includes a product term array and a sum term array. The product term array is coupled to the sum term array via a control transistor. A gate electrode of the control transistor is coupled to an output of the product term array, and a source (or drain) electrode is coupled to an input end of the sum term array. A drain (or source) electrode of the control transistor is coupled to a power source. N-channel type transistors are employed in the product term and the sum term arrays, while a P-channel type transistor is employed as the control transistor.
Inventors
- 👤 Masahiko Kashimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
56 words
A programmable logic array circuit comprising a product term array receiving input signals, a sum term array deriving output signals, and control transistors having control electrodes coupled to output ends of said product term array, the source-drain paths of said control transistors being coupled between input ends of said sum term array and a power source.
Claim 2
Dependent Claim
56 words
A programmable logic array circuit comprising a product term array receiving input signals, a sum term array deriving output signals, and control transistors having control electrodes coupled to output ends of said product term array, the source-drain paths of said control transistors being coupled between input ends of said sum term array and a power source.
Claim 3
Dependent Claim
33 words
A circuit as claimed in claim 1, in which N-channel transistors are employed in said product term array and in said sum term array, and P-channel transistors are employed as said control transistors.
Claim 4
Dependent Claim
23 words
A circuit as claimed in claim 1, further comprising a precharge means for charging product term output ends of said product term array.
Claim 5
Dependent Claim
31 words
A circuit as claimed in claim 1, further comprising a sampling circuit coupled to said product term array, said sampling circuit having transistos which are turned on in a sampling period.
Claim 6
Dependent Claim
137 words
A programmable logic array for connection to first and second voltage sources comprising: a product term array in which N-channel transistors are employed, a sum term array in which N-channel transistors are employed, a sampling circuit coupled to said product term array for coupling said product term array to said first voltage source in a sampling period, a first precharge circuit coupled to said product term array for charging sum term output ends in a precharge period, means for selectively coupling input ends of said sum term array to said second voltage source in said sampling period, and means coupled to said product term output ends for controlling said coupling means for supplying a predetermined potential to said input ends of said sum term array according to output potentials at output ends of said product term array.
Claim 7
Dependent Claim
137 words
A programmable logic array for connection to first and second voltage sources comprising: a product term array in which N-channel transistors are employed, a sum term array in which N-channel transistors are employed, a sampling circuit coupled to said product term array for coupling said product term array to said first voltage source in a sampling period, a first precharge circuit coupled to said product term array for charging sum term output ends in a precharge period, means for selectively coupling input ends of said sum term array to said second voltage source in said sampling period, and means coupled to said product term output ends for controlling said coupling means for supplying a predetermined potential to said input ends of said sum term array according to output potentials at output ends of said product term array.
Claim 8
Dependent Claim
39 words
A circuit as claimed in claim 5, further comprising means coupled to said input ends of said sum term array for coupling said input ends of said sum term array to said first voltage source in said precharge period.
References Cited (Backward Citations)
US3866186A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-27 | 1990-10-27 | 1991-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-27 | 1994-10-27 | 1995-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-27 | 1998-10-27 | 1999-04-28 | $7700.00 | Window Closed / Lapsed |