Patent US4949341A successfully refreshed from Google Patents.
US4949341A
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Built-in self test method for application specific integrated circuit libraries
Assignee: Motorola Solutions Inc
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Filing: 1988-10-28
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Granted: 1990-08-14
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Expires: 2008-10-28
Abstract
Abstract A design and method of exhaustively verifying the boolean functionality of both combinational and sequential cells for Application Specific Integrted Circuit gate array and standard cell libraries is provided. A single integrated circuit includes a plurality of cells or macros from the library. A Gray code generator provides a plurality of Gray code signals to the cells in response to a binary counter. The binary and Gray code signals stimulate each state of each cell. A multiplexed output indicates the functionality of each state.
Inventors
- 👤 David E. Lopez
- 👤 Tomas Colunga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:16
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813; G01R31/3185; G01R31/318516
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
123 words
A circuit for testing a plurality of logic states of each of a plurality of cells, said circuit comprising: first means for generating a plurality of binary signals; second means reponsive to said plurality of binary signals for converting said binary signals into Gray code signals, said binary and Gray code signals being sequentially applied to the plurality of cells of producing a plurality of input stimuli thereat to generate the plurality of logic states within the plurality of cells; and third means coupled to the plurality of cells for providing an output in response to each of the plurality of logic states, wherein said output can be utilized to generate a truth table to test the functionality of the plurality of cells.
Claim 2
Dependent Claim
123 words
A circuit for testing a plurality of logic states of each of a plurality of cells, said circuit comprising: first means for generating a plurality of binary signals; second means reponsive to said plurality of binary signals for converting said binary signals into Gray code signals, said binary and Gray code signals being sequentially applied to the plurality of cells of producing a plurality of input stimuli thereat to generate the plurality of logic states within the plurality of cells; and third means coupled to the plurality of cells for providing an output in response to each of the plurality of logic states, wherein said output can be utilized to generate a truth table to test the functionality of the plurality of cells.
Claim 3
Dependent Claim
25 words
The circuit according to claim 1 further comprising fourth means coupled to said first and second means for monitoring said binary and Gray code signals.
Claim 4
Dependent Claim
37 words
The circuit according to claim 2 further comprising fifth means coupled between said first and second means for providing a specific binary and Gray code signal for establishing a specific logic state for said cells plurality of.
Claim 5
Dependent Claim
33 words
The circuit according to claim 1 wherein said first means comprises: a clock terminal; a reset terminal; and a binary counter coupled between said second means and both said clock and reset terminal.
Claim 6
Dependent Claim
48 words
The circuit according to claim 4 wherein said second means comprises: a Gray code counter; a synchronization circuit coupled between said Gray code counter and said plurality of cells and coupled to said reset terminal; and a delay circuit coupled between said clock terminal and said synchronization circuit.
Claim 7
Dependent Claim
34 words
The circuit according to claim 5 wherein said fourth means comprises a first multiplexer coupled to said binary counter and said synchronization circuit for providing said binary and Gray code signals as an output.
Claim 8
Dependent Claim
33 words
The circuit according to claim 6 wherein said fifth means comprises a second multiplexer coupled to receive a specific combination of binary and Gray code signals and coupled to said Gray code counter.
Claim 9
Dependent Claim
35 words
The circuit according to claim 7 wherein said third means comprises at least one third multiplexer coupled to said plurality of cells for providing an output for each logic state of said plurality of cells.
Claim 10
Dependent Claim
67 words
The circuit according to claim 7 further comprising a bidirectional switch coupled to said first and second multiplexers for selectively providing the binary signals provided by said binary counter and Gray code signals provided by said Gray code counter as an output, and for receiving specific binary and Gray code signals as an input and providing said specific binary and Gray code signals to said second multiplexer.
Claim 11
Dependent Claim
125 words
An integrated circuit including circuitry for verifying the boolean functionality of a plurality of cells on said integrated circuit, said circuitry comprising: first means for generating a plurality of binary signals; second means responsive to said plurality of binary signals for converting said binary signals into Gray code signals, said binary and Gray code signals being sequentially applied to the plurality of cells for producing a plurality of input stimuli thereat to generate a plurality of logic states within the plurality of cells; and third means coupled to the plurality of cells for providing an output in response to each said plurality of logic states, wherein said output can be utilized to generate a truth table to test the functionality of the plurality of cells.
Claim 12
Dependent Claim
125 words
An integrated circuit including circuitry for verifying the boolean functionality of a plurality of cells on said integrated circuit, said circuitry comprising: first means for generating a plurality of binary signals; second means responsive to said plurality of binary signals for converting said binary signals into Gray code signals, said binary and Gray code signals being sequentially applied to the plurality of cells for producing a plurality of input stimuli thereat to generate a plurality of logic states within the plurality of cells; and third means coupled to the plurality of cells for providing an output in response to each said plurality of logic states, wherein said output can be utilized to generate a truth table to test the functionality of the plurality of cells.
Claim 13
Dependent Claim
26 words
The integrated circuit according to claim 10 further comprising fourth means coupled to said first and second means for monitoring said binary and Gray code signals.
Claim 14
Dependent Claim
38 words
The integrated circuit according to claim 11 further comprising fifth means coupled between said first and second means for providing a specific binary and Gray code signal for establishing a specific logic state for said cells plurality of.
Claim 15
Dependent Claim
34 words
The integrated circuit according to claim 10 wherein said first means comprises: a clock pad; a reset pad; and a binary counter coupled between said second means and both said clock and reset pads.
Claim 16
Dependent Claim
49 words
The integrated circuit according to claim 13 wherein said second means comprises: a Gray code counter; a synchronization circuit coupled between said Gray code counter and said plurality of cells and coupled to said reset pad; and a delay circuit coupled between said clock pad and said synchronization circuit.
Claim 17
Dependent Claim
35 words
The integrated circuit according to claim 14 wherein said fourth means comprises a first multiplexer coupled to said binary counter and said synchronization circuit for providing said binary and Gray code signals as an output.
Claim 18
Dependent Claim
34 words
The integrated circuit according to claim 15 wherein said fifth means comprises a second multiplexer coupled to receive a specific combination of binary and Gray code signals and coupled to said Gray code counter.
Claim 19
Dependent Claim
35 words
The circuit according to claim 16 wherein said third means comprises at least one third multiplexer coupled to said plurality of cells for providing an output for each logic state of said plurality of cells.
Claim 20
Dependent Claim
68 words
The integrated circuit according to claim 16 further comprising a bidirectional switch coupled to said first and second multiplexers for selectively providing the binary signals provided by said binary counter and Gray code signals provided by said Gray code counter as an output, and for receiving specific binary and Gray code signals as an input and providing said specific binary and Gray code signals to said second multiplexer.
Claim 21
Independent Claim
117 words
A method of verifying the boolean functionality of a plurality of cells on an integrated circuit, said method comprising the steps of: generating a plurality of binary signals; generating a plurality of Gray code signals in response to the binary signals; applying said binary and Gray code signals to the plurality of cells for producing a plurality of input stimuli thereat wherein a plurality of logic states within the plurality of cells are produced in response to said plurality of input stimuli; and providing an output signal in response to each said plurality of logic states wherein said output signal can be utilized to generate a truth table to test the functionality of the plurality of cells.
Claim 22
Independent Claim
117 words
A method of verifying the boolean functionality of a plurality of cells on an integrated circuit, said method comprising the steps of: generating a plurality of binary signals; generating a plurality of Gray code signals in response to the binary signals; applying said binary and Gray code signals to the plurality of cells for producing a plurality of input stimuli thereat wherein a plurality of logic states within the plurality of cells are produced in response to said plurality of input stimuli; and providing an output signal in response to each said plurality of logic states wherein said output signal can be utilized to generate a truth table to test the functionality of the plurality of cells.
Claim 23
Dependent Claim
18 words
The method according to claim 19 further comprising the step of monitoring the binary and Gray code signals.
Claim 24
Dependent Claim
32 words
The method according to claim 20 further comprising the step of inputing a specific combination of binary and Gray code signals for testing a specific logic state for the cells plurality of.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-13 | 1994-02-12 | 1994-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-13 | 1998-02-12 | 1998-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-13 | 2002-02-12 | 2002-08-14 | $7700.00 | Window Closed / Lapsed |