US4358847A
Expired / Lapsed
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Electrical circuit test apparatus and method
Assignee: Lehigh University
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Filing: 1980-09-02
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Granted: 1982-11-09
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Expires: 2000-09-02
Abstract
Abstract An electrical circuit test apparatus and method are disclosed for detecting faults in n-input combinational circuitry. The testing is performed by the verification of the Walsh coefficients. This is an alternative to the usual Boolean based techniques. To implement the Walsh coefficient verification, a reversible counter is utilized in conjunction with a driving counter, a parity indicating means, and minor control circuitry. The output signal from the unit under test is compared with the parity signal derived from the driving counter, and where there is correspondence, the reversible counter is actuated in one direction. Where they are dissimilar, the reversible counter counts in the opposite direction. A circuit is considered faulty where the final indication in the reversible counter is zero. It has been found that the Walsh spectrum of any given combination logic function f(x) of n independent variables x1 to xn consists of a series of 2n integer numbers, the magnitude and sign of which constitute the spectral coefficient values of f(x). Therefore, because the spectral coefficient values define the output function uniquely, the values for a network with an output fault will differ from these without fault.
Inventors
- 👤 Alfred K. Susskind
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:08
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31935
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
237 words
Apparatus for testing an n-input combinational circuit comprising (a) an input signal pattern means for generating a plurality of electrical input signal patterns, said plurality consisting of the set of all binary numbers that can be formed from n digits, said means adapted to address each of said signal patterns sequentially to the input leads of a circuit to be tested, (b) a parity signal generating means for emitting a parity signal responsive to each input signal pattern generated by said input signal means, said parity signal being 0 to 1 and being indicative of whether the number of zeros in each of said input signal patterns is odd or even, (c) reversible counter means adapted to receive from a circuit under test, an output signal either 0 or 1 for each input signal pattern addressed thereto and comparing the corresponding parity signal therewith, said reversible counter means including arithmetic scoring means for cumulatively either (1) if said parity signal is one for an even number of zeros in an input signal pattern, adding a one each time said output signal and parity signal are the same, subtracting a one each time they are different, or (2) if said parity signal is 0 for an even number of zeros in an output signal pattern, adding a one each time said output signal and parity signal are different and substracting a one each time they are the same.
Claim 2
Dependent Claim
237 words
Apparatus for testing an n-input combinational circuit comprising (a) an input signal pattern means for generating a plurality of electrical input signal patterns, said plurality consisting of the set of all binary numbers that can be formed from n digits, said means adapted to address each of said signal patterns sequentially to the input leads of a circuit to be tested, (b) a parity signal generating means for emitting a parity signal responsive to each input signal pattern generated by said input signal means, said parity signal being 0 to 1 and being indicative of whether the number of zeros in each of said input signal patterns is odd or even, (c) reversible counter means adapted to receive from a circuit under test, an output signal either 0 or 1 for each input signal pattern addressed thereto and comparing the corresponding parity signal therewith, said reversible counter means including arithmetic scoring means for cumulatively either (1) if said parity signal is one for an even number of zeros in an input signal pattern, adding a one each time said output signal and parity signal are the same, subtracting a one each time they are different, or (2) if said parity signal is 0 for an even number of zeros in an output signal pattern, adding a one each time said output signal and parity signal are different and substracting a one each time they are the same.
Claim 3
Dependent Claim
70 words
Apparatus, as recited in Claim 1, further including means connected between the input signal pattern means and the reversible counter means for zeroing said reversible counter means prior to activation of said input signal means and for holding and signaling as an output, the cumulative result of said adding and subtracting in said reversible counter after said input signal means has generated all of said plurality of input signal patterns.
Claim 4
Dependent Claim
152 words
Apparatus, as recited in claim 1, further including a selection means for selecting a predetermined subset of input leads consisting of less than all of said input leads and for signaling an additional reversible counter with selected parity signals corresponding to said predetermined lead subset, said additional reversible counter means including means for comparing said selected parity signals with the corresponding circuit output signals and arithmetic scoring means for cumulatively either (1) if said parity signal is one for a number of zeros in an input signal pattern, adding a one each time said output signal and parity signal are the same, subtracting a one each time they are different, or (2) if said parity signal is 0 for an odd number of zeros in an output signal pattern, adding a one each time said output signal and parity signal are different and subtracting a one each time they are the same.
Claim 5
Dependent Claim
41 words
Apparatus, as recited in claim 3, wherein said additional reversible counter is the same as said first reversible counter, said apparatus further including sequencing means for the separate sequential use of said reversible counter as said first and said additional counter.
Claim 6
Dependent Claim
39 words
Apparatus, as recited in claim 1, further including test result indicating means, responsive to a 0 signal from said reversible counter at the conclusion of the test, for indicating that a circuit under test is indicated to be defective.
Claim 7
Dependent Claim
54 words
Apparatus, as recited in claim 5, further including test result indicating means for comparing the number result in said second reversible counter at the conclusion of the test with a predetermined correct test result number and for indicating, in response thereto, that a circuit under test is indicated to be defective or not defective.
Claim 8
Dependent Claim
38 words
Apparatus, as recited in any of claims 1 to 6, wherein said apparatus comprises an electrical test circuit permanently attached to and sharing a common mounting with a second circuit adapted to be tested by said first circuit.
Claim 9
Dependent Claim
117 words
Method for testing an n-input combinational circuit comprising (a) sequentially generating and addressing to the n-input leads of a circuit under test, a plurality of electrical input signal patterns consisting of a set of all binary numbers that can be formed from n digits, (b) generating a parity signal corresponding to each of said input signal patterns, said parity signal being 0 to 1, (c) comparing the output of said circuit to the parity signal for each corresponding input signal and either incrementing or decrementing a reversible counter, and (d) examining the reversible counter at the conclusion of the test and determining that the circuit is acceptable or not acceptable on the basis of the counter contents.
Claim 10
Dependent Claim
117 words
Method for testing an n-input combinational circuit comprising (a) sequentially generating and addressing to the n-input leads of a circuit under test, a plurality of electrical input signal patterns consisting of a set of all binary numbers that can be formed from n digits, (b) generating a parity signal corresponding to each of said input signal patterns, said parity signal being 0 to 1, (c) comparing the output of said circuit to the parity signal for each corresponding input signal and either incrementing or decrementing a reversible counter, and (d) examining the reversible counter at the conclusion of the test and determining that the circuit is acceptable or not acceptable on the basis of the counter contents.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-11-08 | 1986-05-10 | 1986-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-08 | 1990-05-10 | 1990-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-08 | 1994-05-10 | 1994-11-09 | $7700.00 | Window Closed / Lapsed |