Patent US4949149A successfully refreshed from Google Patents.
US4949149A
Expired / Lapsed
US
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Semicustom chip whose logic cells have narrow tops and wide bottoms
Assignee: Unisys Corp
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Filing: 1987-03-31
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Granted: 1990-08-14
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Expires: 2007-03-31
Abstract
Abstract A logic cell, for use in a semicustom chip, is comprised of a plurality of transistors that are integrated into a semiconductor substrate and are interconnected within the cell to perform a logic function. This cell has sidewalls which define the space in the chip which contains all the transistors and their interconnections within the cell; at least one of the sidewalls is shaped to include a step which gives the cell a narrow top and a wide bottom; and one or more of the cell's transistors lies below the step in the wide bottom of the cell. Many of these cells are arranged in spaced apart rows on the semicustom chip in which the narrow tops of the cell line up. Conductors which interconnect the cells are disposed in the space between the narrow tops of the cells and over the transistors in the wide bottoms of the cells. Using this architecture, the density with which a logic cell is integrated to a semicustom chip is improved more than 100%.
Inventors
- 👤 Fernando W. Arraut
- 👤 Laszlo V. Gal
- 👤 Robert C. H. Shen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:37
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/901; H10D84/903; H10D84/907; H10W; H10W72/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
166 words
A semicustom chip which is comprised of: a plurality of logic cells that are integrated into a single semiconductor substrate; each of said cells containing input terminals, an output terminal, and transistors which are interconnected within the cell to generate an output signal on said output terminal as a logical function of input signals on said input terminals; and said cells being arranged in rows which are spaced apart from each other; wherein some of said cells have step-shaped sidewalls that form respective cell tops of a width W R which are aligned in said rows, and form respective cell bottoms which due to said step are substantially wider than said width W R ; conductors, lying in a plane in the space between said rows over said step in said wide cell bottoms, which carry signals between said terminals of said cells; and said wide cell bottoms containing transistors for their corresponding logic cells and extending those transistors parallel to said plane beneath said conductors.
Claim 2
Dependent Claim
166 words
A semicustom chip which is comprised of: a plurality of logic cells that are integrated into a single semiconductor substrate; each of said cells containing input terminals, an output terminal, and transistors which are interconnected within the cell to generate an output signal on said output terminal as a logical function of input signals on said input terminals; and said cells being arranged in rows which are spaced apart from each other; wherein some of said cells have step-shaped sidewalls that form respective cell tops of a width W R which are aligned in said rows, and form respective cell bottoms which due to said step are substantially wider than said width W R ; conductors, lying in a plane in the space between said rows over said step in said wide cell bottoms, which carry signals between said terminals of said cells; and said wide cell bottoms containing transistors for their corresponding logic cells and extending those transistors parallel to said plane beneath said conductors.
Claim 3
Dependent Claim
25 words
A semicustom chip according to claim 1 wherein some of said wide cell bottoms are at least 20% wider than said width W R .
Claim 4
Dependent Claim
39 words
A semicustom chip according to claim 2 wherein some of said cells have two oppositely facing stepped sidewalls that contain transistors which extend beneath said conductors in the space adjacent of the respective row in which those cells lie.
Claim 5
Dependent Claim
30 words
A semicustom chip according to claim 2 wherein some of said wide cell bottoms contain transistors which lie in their entirety beneath said conductors in the space between said rows.
Claim 6
Dependent Claim
26 words
A semicustom chip according to claim 2 wherein said conductors between said rows are patterned metal lines which lie on an insulating layer over said transistors.
Claim 7
Dependent Claim
14 words
A semicustom chip according to claim 2 wherein said transistors are field effect transistors.
Claim 8
Dependent Claim
13 words
A semicustom chip according to claim 2 wherein said transistors are bipolar transistors.
Claim 9
Dependent Claim
107 words
A logic cell, for use in a semicustom chip, which is comprised of: a plurality of transistors that are integrated into a single semiconductor substrate and are interconnected within said cell to perform a logic function; said cell having sidewalls which define a space in said chip which contains all of said transistors and their intracell connections; at least one of said sidewalls being shaped to include a step which gives said cell a narrow top and a wide bottom which is at least 40% wider than said top; and at least one of said transistors lying below said step in the wide bottom of said cell.
Claim 10
Dependent Claim
107 words
A logic cell, for use in a semicustom chip, which is comprised of: a plurality of transistors that are integrated into a single semiconductor substrate and are interconnected within said cell to perform a logic function; said cell having sidewalls which define a space in said chip which contains all of said transistors and their intracell connections; at least one of said sidewalls being shaped to include a step which gives said cell a narrow top and a wide bottom which is at least 40% wider than said top; and at least one of said transistors lying below said step in the wide bottom of said cell.
Claim 11
Dependent Claim
33 words
A logic cell according to claim 8 wherein two of said sidewalls are each shaped to include a step, and respective transistors lie below both steps in the wide bottom of said cell.
Claim 12
Dependent Claim
21 words
A logic cell according to claim 8 wherein said wide bottom of said cell includes doped regions in said semiconductor substrate.
Claim 13
Dependent Claim
28 words
A logic cell according to claim 8 wherein at least one of said transistors lies in its entirety below said step in the wide bottom of said cell.
Claim 14
Dependent Claim
14 words
A logic cell according to claim 8 wherein said transistors are field effect transistors.
Claim 15
Dependent Claim
13 words
A logic cell according to claim 8 wherein said transistors are bipolar transistors.
References Cited (Backward Citations)
US4006492A
Cited
US4381201A
Cited
US4500905A
Cited
US4644382A
Cited
US4589007A
Cited
JPS6016443A
Cited
US4646266A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-13 | 1994-02-12 | 1994-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-13 | 1998-02-12 | 1998-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-13 | 2002-02-12 | 2002-08-14 | $7700.00 | Window Closed / Lapsed |