Patent US3868083A successfully refreshed from Google Patents.
Patent US4949136A successfully refreshed from Google Patents.
US4949136A
Expired / Lapsed
US
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Submicron lightly doped field effect transistors
Assignee: University of Connecticut
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Filing: 1988-06-09
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Granted: 1990-08-14
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Expires: 2008-06-09
Abstract
Abstract A lightly doped field effect transistor has a central gate portion and source and drain portions spaced to opposite sides thereof and each having a heavily doped contact section and a sidewall spacer portion between the gate portion and contact section. Each of the source and drain portions also has a lightly doped sheath with a first portion extending to a first depth about the sides of and below the contact section, and an extension of lesser depth extending under the spacer portion to the gate portion, thus providing a stepped configuration for the sheath in cross section. The sheaths have an impurity doping concentration which is 10 2 -10 4 lower than the impurity doping concentration in the contact sections.
Inventors
- 👤 Faquir C. Jain
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:02
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
230 words
A silicon lightly doped field effect transistor having: (a) a central gate portion; (b) a source portion to one side of said gate portion and having a heavily doped contact section spaced from said gate portion, a sidewall spacer portion about said gate portion and between said gate portion and contact section, and a lightly doped sheath about the sides and bottom of said heavily doped contact section, said sheath extending to a first depth about the sides of and below said contact section and having an extension of lesser depth extending from below said spacer portion to said gate portion, thereby providing a stepped configuration in cross section; and (c) a drain portion to the opposite side of said gate portion and having a heavily doped contact section spaced from said gate portion, a sidewall spacer portion about said gate portion and between said gate portion and contact section, and a lightly doped sheath about the sides and bottom of said heavily doped contact section, said sheath extending to a first depth about the sides of and below said contact section and having an extension of lesser depth extending from below said spacer portion to said gate portion, thereby providing a stepped configuration in cross section, said sheaths having an impurity doping concentration 10 2 - 4 lower than the impurity doping concentration in the heavily doped contact sections.
Claim 2
Dependent Claim
230 words
A silicon lightly doped field effect transistor having: (a) a central gate portion; (b) a source portion to one side of said gate portion and having a heavily doped contact section spaced from said gate portion, a sidewall spacer portion about said gate portion and between said gate portion and contact section, and a lightly doped sheath about the sides and bottom of said heavily doped contact section, said sheath extending to a first depth about the sides of and below said contact section and having an extension of lesser depth extending from below said spacer portion to said gate portion, thereby providing a stepped configuration in cross section; and (c) a drain portion to the opposite side of said gate portion and having a heavily doped contact section spaced from said gate portion, a sidewall spacer portion about said gate portion and between said gate portion and contact section, and a lightly doped sheath about the sides and bottom of said heavily doped contact section, said sheath extending to a first depth about the sides of and below said contact section and having an extension of lesser depth extending from below said spacer portion to said gate portion, thereby providing a stepped configuration in cross section, said sheaths having an impurity doping concentration 10 2 - 4 lower than the impurity doping concentration in the heavily doped contact sections.
Claim 3
Dependent Claim
29 words
The transistor of claim 1 in which the lightly doped sheaths are of n - conductivity type and the heavily doped contact sections are of the n + type.
Claim 4
Dependent Claim
29 words
The transistor of claim 1 in which the lightly doped sheaths are of p - conductivity type and the heavily doped contact sections are of the n + type.
Claim 5
Dependent Claim
30 words
The transistor of claim 1 including a separate halo layer extending about and below each of said sheaths and of a conductivity opposite to that of said lightly doped sheaths.
Claim 6
Dependent Claim
281 words
A CMOS transistor pair structure comprising a spaced lightly doped field effect pair of transistors each having: (a) a central gate portion; (b) a source portion to one side of said gate portion and having a heavily doped contact section spaced from said gate portion, a sidewall spacer portion about said gate portion and between said gate portion and contact section, and a lightly doped sheath about the sides and bottom of said heavily doped contact section, said sheath extending to a first depth about the sides of and below said contact section and having an extension of lesser depth extending from below said spacer portion to said gate portion, thereby providing a stepped configuration in cross section: and (c) a drain portion to the opposite side of said gate portion and having a heavily doped contact section spaced from said gate portion, a sidewall spaced portion about said gate portion and between said gate portion and contact section, and a lightly doped sheath about the sides and bottom of said heavily doped contact section, said sheath extending to a first depth about the sides of and below said contact section and having an extension of lesser depth extending from below said spacer portion to said gate portion, thereby providing a stepped configuration in cross section, the lightly doped sheaths of one of said transistors being of n - conductivity type and 10 2 -10 4 lower in impurity doping concentration than the heavily doped n + sections, the lightly doped sheaths of the other of said transistors being of p - conductivity type and 10 2 -10 4 lower in impurity doping concentration than the heavily doped p + sections.
Claim 7
Dependent Claim
281 words
A CMOS transistor pair structure comprising a spaced lightly doped field effect pair of transistors each having: (a) a central gate portion; (b) a source portion to one side of said gate portion and having a heavily doped contact section spaced from said gate portion, a sidewall spacer portion about said gate portion and between said gate portion and contact section, and a lightly doped sheath about the sides and bottom of said heavily doped contact section, said sheath extending to a first depth about the sides of and below said contact section and having an extension of lesser depth extending from below said spacer portion to said gate portion, thereby providing a stepped configuration in cross section: and (c) a drain portion to the opposite side of said gate portion and having a heavily doped contact section spaced from said gate portion, a sidewall spaced portion about said gate portion and between said gate portion and contact section, and a lightly doped sheath about the sides and bottom of said heavily doped contact section, said sheath extending to a first depth about the sides of and below said contact section and having an extension of lesser depth extending from below said spacer portion to said gate portion, thereby providing a stepped configuration in cross section, the lightly doped sheaths of one of said transistors being of n - conductivity type and 10 2 -10 4 lower in impurity doping concentration than the heavily doped n + sections, the lightly doped sheaths of the other of said transistors being of p - conductivity type and 10 2 -10 4 lower in impurity doping concentration than the heavily doped p + sections.
Claim 8
Dependent Claim
29 words
The transistor of claim 5 including a separate halo layer extending about and below encasing said sheaths and of a conductivity opposite to that of the lightly doped sheaths.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-13 | 1994-02-12 | 1994-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-13 | 1998-02-12 | 1998-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-13 | 2002-02-12 | 2002-08-14 | $7700.00 | Window Closed / Lapsed |