Direct digital locked loop

Claim 2

A timing device, comprising: an oscillator for generating a first signal having a first frequency; digital synthesizer means coupled to said oscillator for generating a second signal having a second frequency related to said first frequency; digital phase detection means coupled to said synthesizer means for measuring the change in phase difference between said second signal and a third signal supplied to said digital phase detection means, said digital phase detection means comprising at least one counter coupled to said third signal; said digital phase detection means varying said second frequency in response to a change in an output signal of said counter, said output of said counter corresponding to said changes in said phase difference between said second and third signals.

Claim 3

The device of claim 1 wherein said oscillator operates at a fixed frequency.

Claim 4

The device of claim 1 wherein said digital phase detection means comprises first and second counters and a microprocessor, wherein said first counter is coupled to said synthesizer, said second counter is coupled to said third signal, and said microprocessor is coupled to said counters and said synthesizer such that said microprocessor reads a value in each of said counters and provides a fourth signal to said synthesizer according to the values of said counters.

Claim 5

The device of claim 3 wherein said microprocessor generates said fourth signal by means of data stored in a look-up table coupled to said microprocessor.

Claim 6

The device of claim 4 wherein said look-up table comprises a non-volatile memory.

Claim 7

The device of claim 1 wherein said oscillator generates a signal having a frequency approximately equal to 10.24 MHz.

Claim 8

A digital locked loop for use as a slave clock in an electronic system having a master clock which generates a master clock signal coupled to at least one slave clock comprising: an oscillator for generating a first signal having a first frequency; a digital synthesizer means coupled to said oscillator for accepting a numerical value (N) from a microprocessor coupled to said digital synthesizer means and generating a second signal having a second frequency, said second frequency being a predetermined function of said first frequency and N; a first counter means coupled to the output of said synthesizer; a second counter means coupled to said master clock and a latch means, said latch means also being coupled to said first counter means and said microprocessor, said second counter means generating an enabling signal after counting a predetermined number of pulses in said master clock signal; said latch means storing a value of said first counter upon receiving said enabling signal from said second counter and providing said stored value to said microprocessor, said microprocessor in turn generating a new value of N in response to changes in said stored value such that said frequency of said second signal varies to be substantially equal to a frequency of said master clock signal.

Claim 9

A digital locked loop for use as a slave clock in an electronic system having a master clock which generates a master clock signal coupled to at least one slave clock comprising: an oscillator for generating a first signal having a first frequency; a digital synthesizer means coupled to said oscillator for accepting a numerical value (N) from a microprocessor coupled to said digital synthesizer means and generating a second signal having a second frequency, said second frequency being a predetermined function of said first frequency and N; a first counter means coupled to the output of said synthesizer; a second counter means coupled to said master clock and a latch means, said latch means also being coupled to said first counter means and said microprocessor, said second counter means generating an enabling signal after counting a predetermined number of pulses in said master clock signal; said latch means storing a value of said first counter upon receiving said enabling signal from said second counter and providing said stored value to said microprocessor, said microprocessor in turn generating a new value of N in response to changes in said stored value such that said frequency of said second signal varies to be substantially equal to a frequency of said master clock signal.

Claim 10

The device of claim 7 wherein said oscillator is nonadjustable.

Claim 11

The device of claim 7 wherein N is chosen such that said second frequency is substantially equal to said frequency of said master clock signal.

Claim 12

The device of claim 7 wherein said microprocessor generates a predetermined value of N in the absence of said master clock signal.

Claim 13

The device of claim 7 wherein said microprocessor keeps N fixed at its most recent value in the absence of said signal from said maser clock.

Claim 14

The device of claim 7 wherein said first frequency is approximately equal to 10.24 MHz.

Claim 15

The device of claim 7 wherein said first and said second counter means both store a same maximum value.

Claim 16

The device of claim 13 wherein said predetermined number of pulses is equal to said maximum value.

Claim 17

The device of claim 14 wherein said enabling signal is an overflow signal generated by said second counter means after said second counter means has counted a number of pulses in said master clock signal equal to said maximum value.

Claim 18

The device of claim 15 wherein said first counter means stores a second maximum value, said second maximum value being equal to said first maximum value.

Claim 19

The device of claim 15 wherein said first maximum value is 2 16 .

Claim 20

The device of claim 7 wherein said predetermined function is defined as follows: ##EQU2## wherein X is the number of binary digits (bits) used by the synthesizer; wherein F osc is equal to said first frequency, and F out is equal to said second frequency.