Patent US4947136A successfully refreshed from Google Patents.
US4947136A
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Variable gain distributed amplifier
Assignee: Lockheed Martin Corp
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Filing: 1989-09-18
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Granted: 1990-08-07
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Expires: 2009-09-18
Abstract
Abstract The invention relates to a variable gain distributed amplifier for use at microwave frequencies, and fabricated in a monolithic microwave integrated circuit format. In the amplifier, the attenuation is varied, based upon digital control of a dual gate segmented FET. The amplifier has a nearly flat insertion phase and amplitude response, and an insertion phase response that varies only slightly between gain settings. The amplifier employs segmented dual gate field effect transistors as the gain elements, having their signal input and signal output electrodes which provide shunt capacities (C G1S , C DS ) interconnected with serial inductances to form separate low pass transmission lines having relatively high cut-off frequencies. The amplifier has means to insure stability and uses Chebyshef equal ripple techniques to linearize the amplitude and insertion phase response.
Inventors
- 👤 David R. Helms
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:36
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0088; H03F; H03F3/00; H03F3/60; H03F3/605; H03F3/607; H03G3/00; H03G3/001; H10; H10D; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/257
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
357 words
A variable gain distributed amplifier comprising (A) a signal input terminal for application of signals to the distributed amplifier; (B) m segmented dual gate field effect transistors (SDGFETs), each similarly subdivided into n selectively activated segments, each SDGFET having source, drain, and signal gate electrodes common to all segments with corresponding manifolds, and a control gate electrode divided into n segments disposed between the signal gate electrode and the drain electrode; and n control gate terminals, each control gate terminal selectively activating an associated segment of the SDGFET, each SDGFET segment having a predetermined width to effect a desired increment in SDGFET transconductance (G m ) when activated, the signal gate manifold to source capacitance (C G1S ) and the drain manifold to source capacitance (C DS ) remaining constant and substantially unaffected by segment inactivation; (C) a first wideband low pass transmission line means for propagating signals from said signal input terminal to said successive signal gate manifolds at which power division occurs, said first transmission line means consisting of m successive shunt capacities to signal ground provided by the signal gate to source capacities (C G1S ) of said SDGFETs, and (m-1) serial first inductances interconnecting said signal gate manifolds in succession to effect a more wideband response and higher cut-off frequency; (D) a signal output terminal for the distributed amplifier; (E) a second wideband low pass transmission line means into which signals from said successive drain manifolds are constructively combined for propagation to said signal output terminal, said second transmission line means comprising m successive shunt capacities to signal ground provided by the drain to source capacities (C DS ) of said SDGFETs, and (m-1) serial second inductances interconnecting m nodes in succession, to each of which a corresponding drain manifold is coupled to effect a more wideband response and higher cut-off frequency; and (F) a control network connected to said control terminals of said SDGFETs for selectively activating corresponding segments in each of said SDGFETs to effect equal G m s in each SDGFET, the state of activation of said SDGFETs having a minimum effect upon the phase response of said distributed amplifier.
Claim 2
Dependent Claim
357 words
A variable gain distributed amplifier comprising (A) a signal input terminal for application of signals to the distributed amplifier; (B) m segmented dual gate field effect transistors (SDGFETs), each similarly subdivided into n selectively activated segments, each SDGFET having source, drain, and signal gate electrodes common to all segments with corresponding manifolds, and a control gate electrode divided into n segments disposed between the signal gate electrode and the drain electrode; and n control gate terminals, each control gate terminal selectively activating an associated segment of the SDGFET, each SDGFET segment having a predetermined width to effect a desired increment in SDGFET transconductance (G m ) when activated, the signal gate manifold to source capacitance (C G1S ) and the drain manifold to source capacitance (C DS ) remaining constant and substantially unaffected by segment inactivation; (C) a first wideband low pass transmission line means for propagating signals from said signal input terminal to said successive signal gate manifolds at which power division occurs, said first transmission line means consisting of m successive shunt capacities to signal ground provided by the signal gate to source capacities (C G1S ) of said SDGFETs, and (m-1) serial first inductances interconnecting said signal gate manifolds in succession to effect a more wideband response and higher cut-off frequency; (D) a signal output terminal for the distributed amplifier; (E) a second wideband low pass transmission line means into which signals from said successive drain manifolds are constructively combined for propagation to said signal output terminal, said second transmission line means comprising m successive shunt capacities to signal ground provided by the drain to source capacities (C DS ) of said SDGFETs, and (m-1) serial second inductances interconnecting m nodes in succession, to each of which a corresponding drain manifold is coupled to effect a more wideband response and higher cut-off frequency; and (F) a control network connected to said control terminals of said SDGFETs for selectively activating corresponding segments in each of said SDGFETs to effect equal G m s in each SDGFET, the state of activation of said SDGFETs having a minimum effect upon the phase response of said distributed amplifier.
Claim 3
Dependent Claim
61 words
The combination set forth in claim 1, wherein said variable gain distributed amplifier is a monolithic microwave integrated circuit (MMIC), having a substrate, said m SDGFETs being fabricated on said substrate, and said inductances being formed of conductor runs on one surface of said substrate, the other surface thereof having a conductive layer forming said signal ground to support microstrip propagation.
Claim 4
Dependent Claim
62 words
The combination set forth in claim 2, having in addition thereto resistance means coupled between the final signal gate manifold and said signal ground to terminate said first transmission line means to minimize reflections, and resistance means coupled in series with a capacitor between the initial drain manifold and said signal ground to terminate said second transmission line means to minimize reflections.
Claim 5
Dependent Claim
46 words
The combination set forth in claim 2, having in addition thereto, (m-2) series diplexers connected in parallel with portions of said second inductances prior to the last, each diplexer including a serial resistance to de"Q" the associated inductance near the cut-off frequency to avoid amplifier instability.
Claim 6
Dependent Claim
60 words
The combination set forth in claim 4, having in addition thereto m third inductances, each interconnecting successive drain manifolds to the associated nodes and formed of conductor runs disposed over said conductive layer to support microstrip propagation, and wherein said m third inductances are arranged to produce differing delays in electrical degrees to facilitate smoothing the amplifier response below cut-off.
Claim 7
Dependent Claim
32 words
The combination set forth in claim 5, wherein the values of said first inductances, said second inductances, and said third inductances are assigned to form a stagger tuned Chebyshef equal ripple filter.
Claim 8
Dependent Claim
43 words
The combination set forth in claim 6, wherein said serial resistances of said diplexers are insertes between two conductor runs, disposed over said conductive layer to support microstrip propagation at a high characteristic impedance relative to the microstrip propagation by said second inductance.
Claim 9
Dependent Claim
64 words
The combination set forth in claim 7 wherein: the electrical length of the path from drain manifold DM i to DM.sub.(i+1) and the electrical length of the path from signal gate manifold G1M i to G1M.sub.(i+1) are approximately equal at the cut-off frequency, and the electrical length of successive said paths are distributed about 90 electrical degrees to facilitate said Chebyshef equal ripple response.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-06 | 1994-02-05 | 1994-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-06 | 1998-02-05 | 1998-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-06 | 2002-02-05 | 2002-08-07 | $7700.00 | Window Closed / Lapsed |