Method and apparatus for testing digital systems

Claim 5

A method as defined in claim 2, comprising: isolating the boundary register means from systems other than the system under test; and accumulating together within the boundary register means initial contents of the boundary register means and output signals from the system under test to generate input signals for application to the system under test and to generate the test result pattern.

Claim 6

A method as defined in claim 2, comprising: connecting selected terminals of the boundary register means to at least one system other than the system under test; applying signals from the other system to the selected terminals of the boundary register means; and accumulating together the applied signals and output signals from the system under test to generate input signals for application to the system under test and to generate the test result pattern.

Claim 7

A method as defined in claim 1 or claim 2, wherein the boundary register means is also operable as a shift register, the method comprising: configuring the boundary register means as a shift register and shifting a predetermined seed pattern into the boundary register means to intitialize the state of the boundary register means; and configuring the boundary register means as a shift register and shifting the generated test result pattern out of the boundary register means to means for comparing the generated test result pattern with a predetermined test result pattern to compare the generated test result pattern to the predetermined test result pattern.

Claim 8

Test apparatus for testing a digital system having a plurality of system terminals for coupling input signals into the system and output signals out of the system during normal operation of the system, the test apparatus comprising: boundary register means for connection in parallel to at least some of the system terminals, said boundary register means being operable to pass input signals and output signals transparently through the boundary register means while accumulating together said input signals and output signals; means for initializing the state of the digital system and the state of the boundary register means to predetermined states; means for running the digital system through a predetermined number of clock cycles while passing known input signals through the boundary register means into the system and accumulating together within the boundary register means said known input signals and output signals provided by the digital system to generate a test result pattern; and means for comparing the generated test result pattern to a predetermined test result pattern.

Claim 9

Test apparatus for testing a digital system having a plurality of system terminals for coupling input signals into the system and output signals out of the system during normal operation of the system, the test apparatus comprising: boundary register means for connection in parallel to at least some of the system terminals, said boundary register means being operable to pass input signals and output signals transparently through the boundary register means while accumulating together said input signals and output signals; means for initializing the state of the digital system and the state of the boundary register means to predetermined states; means for running the digital system through a predetermined number of clock cycles while passing known input signals through the boundary register means into the system and accumulating together within the boundary register means said known input signals and output signals provided by the digital system to generate a test result pattern; and means for comparing the generated test result pattern to a predetermined test result pattern.

Claim 10

Test apparatus for testing a digital system having a plurality of system terminals for coupling input signals into the system and output signals out of the system during normal operation of the system, the test apparatus comprising: boundary register means for connection in parallel to at least some of the system terminals, said boundary register means being operable to generate input signals and to pass said input signals from the boundary register means to selected system terminals while receiving output signals from selected system terminals and accumulating together said input signals and said output signals; means for initializing the state of the digital system and the state of the boundary register means to predetermined states; means for running the digital system through a predetermined number of clock cycles generate input signals and to pass said input signals from the boundary register means to selected system terminals while receiving output signals from the selected system terminals and accumulating together within the boundary register means said input signals and output signals to generate a test result pattern; and means for comparing the generated test result pattern to a predetermined test result pattern.

Claim 11

Test apparatus for testing a digital system having a plurality of system terminals for coupling input signals into the system and output signals out of the system during normal operation of the system, the test apparatus comprising: boundary register means for connection in parallel to at least some of the system terminals, said boundary register means being operable to generate input signals and to pass said input signals from the boundary register means to selected system terminals while receiving output signals from selected system terminals and accumulating together said input signals and said output signals; means for initializing the state of the digital system and the state of the boundary register means to predetermined states; means for running the digital system through a predetermined number of clock cycles generate input signals and to pass said input signals from the boundary register means to selected system terminals while receiving output signals from the selected system terminals and accumulating together within the boundary register means said input signals and output signals to generate a test result pattern; and means for comparing the generated test result pattern to a predetermined test result pattern.

Claim 12

Test apparatus as defined in claim 7, wherein the boundary register means is operable as a ring register for generating input signals while accumulating together said input signals and output signals received from selected system terminals.

Claim 13

Test apparatus as defined in claim 7, wherein the boundary register means is also operable to pass input signals and output signals transparently through the boundary register means.

Claim 14

Test apparatus as defined in claim 6 or claim 7, wherein the boundary register means is also operable as a shift register to shift predetermined seed patterns into the boundary register means and to shift generated test result patterns out of the boundary register means.

Claim 15

Test apparatus as defined in claim 6 or claim 7, for testing digital systems having a plurality of system input terminals for coupling input signals into the system during normal operation of the system and a plurality of system output terminals for coupling output signals out of the system during normal operation of the system, wherein the boundary register means has: a plurality of parallel output terminals, each for connection in parallel with a respective one of the system input terminals; and a plurality of parallel input terminals, each for connection in parallel with a respective one of the system output terminals.

Claim 16

Test apparatus as defined in claim 6 or claim 7, for testing digital systems having at least one bidirectional system terminal for coupling input signals into the system and output signals out of the system during normal operation of the system, wherein the boundary register means has at least one bidirectional terminal, each bidirectional terminal of the boundary register means for connection in parallel to a respective bidirectional system terminal.

Claim 17

A digital integrated circuit, comprising: a digital system having a plurality of system terminals for coupling input signals into the system and output signals out of the system during normal operation of the system; a plurality of integrated circuit terminals for coupling input signals into the integrated circuit and output signals out of the integrated circuit; and boundary register means connected in parallel between corresponding integrated circuit terminals and system terminals, said boundary register means being operable to pass input signals and output signals transparently through the boundary register means while accumulating together said input signals and output signals.

Claim 18

A digital integrated circuit, comprising: a digital system having a plurality of system terminals for coupling input signals into the system and output signals out of the system during normal operation of the system; a plurality of integrated circuit terminals for coupling input signals into the integrated circuit and output signals out of the integrated circuit; and boundary register means connected in parallel between corresponding integrated circuit terminals and system terminals, said boundary register means being operable to pass input signals and output signals transparently through the boundary register means while accumulating together said input signals and output signals.

Claim 19

A digital integrated circuit, comprising: a digital system having a plurality of system terminals for coupling input signals into the system and output signals out of the system during normal operation of the system; a plurality of integrated circuit terminals for coupling input signals into the integrated circuit and output signals out of the integrated circuit; boundary register means connected in parallel between corresponding integrated circuit terminals and system terminals, said boundary register means being operable in a normal operation mode to pass input signals and output signals transparently through the boundary register means and being operable in a test mode to generate input signals and to pass said input signals from the boundary register to selected system terminals while receiving output signals from selected system terminals and accumulating together said input signals and said output signals.

Claim 20

A digital integrated circuit, comprising: a digital system having a plurality of system terminals for coupling input signals into the system and output signals out of the system during normal operation of the system; a plurality of integrated circuit terminals for coupling input signals into the integrated circuit and output signals out of the integrated circuit; boundary register means connected in parallel between corresponding integrated circuit terminals and system terminals, said boundary register means being operable in a normal operation mode to pass input signals and output signals transparently through the boundary register means and being operable in a test mode to generate input signals and to pass said input signals from the boundary register to selected system terminals while receiving output signals from selected system terminals and accumulating together said input signals and said output signals.

Claim 21

An integrated circuit as defined in claim 13 or claim 14 further comprising: means for initializing the state of the digital system and the state of the boundary register means to predetermined states; means for running the digital system through a predetermined number of clock cycles to generate a test result pattern in the boundary register means; and means for comparing the generated test result pattern to a predetermined test result pattern.

Claim 22

A digital system, comprising: a plurality of digital subsystems, each having a plurality of subsystem terminals for coupling input signals into the subsystem and output signals out of the subsystem during normal operation of the subsystem; and a plurality of boundary registers, a respective boundary register connected in parallel to the subsystem terminals of each subsystem, the boundary registers being interconnected to interconnect the subsystems via the boundary registers, each said boundary register being operable to pass input signals and output signals transparently through the boundary register while accumulating together said input signals and output signals.

Claim 23

A digital system, comprising: a plurality of digital subsystems, each having a plurality of subsystem terminals for coupling input signals into the subsystem and output signals out of the subsystem during normal operation of the subsystem; and a plurality of boundary registers, a respective boundary register connected in parallel to the subsystem terminals of each subsystem, the boundary registers being interconnected to interconnect the subsystems via the boundary registers, each said boundary register being operable to pass input signals and output signals transparently through the boundary register while accumulating together said input signals and output signals.

Claim 24

A digital system, comprising: a plurality of digital subsystems, each having a plurality of subsystem terminals for coupling input signals into the subsystem and output signals out of the subsystem during normal operation of the subsystem; and a plurality of boundary registers, a respective boundary register connected in parallel to the subsystem terminals of each subsystem, the boundary registers being interconnected to interconnect the subsystems, each said boundary register being operable in a normal operation mode to pass input signals and output signals transparently through the boundary register and being operable in a test mode to generate input signals and to pass said input signals from the boundary register to selected subsystem terminals while receiving output signals from selected system terminals and accumulating together said input signals and said output signals.

Claim 25

A digital system, comprising: a plurality of digital subsystems, each having a plurality of subsystem terminals for coupling input signals into the subsystem and output signals out of the subsystem during normal operation of the subsystem; and a plurality of boundary registers, a respective boundary register connected in parallel to the subsystem terminals of each subsystem, the boundary registers being interconnected to interconnect the subsystems, each said boundary register being operable in a normal operation mode to pass input signals and output signals transparently through the boundary register and being operable in a test mode to generate input signals and to pass said input signals from the boundary register to selected subsystem terminals while receiving output signals from selected system terminals and accumulating together said input signals and said output signals.

Claim 26

A digital system as defined in claim 16 or claim 17, further comprising: means for initializing the state of each digital subsystem and the state of each boundary register to predetermined states; means for running the digital subsystems and boundary registers through a predetermined number of clock cycles to generate test result patterns in the boundary registers; and means for comparing the generated test result patterns to a predetermined test result patterns.

Claim 27

A boundary register cell, comprising: a serial input terminal; a serial output terminal; a parallel input terminal; a parallel output terminal; control terminal means; and signal gating and accumulation means operably connected to the serial input terminal, the serial output terminal, the parallel input terminal, the parallel output terminal and the control terminal means, the signal gating and accumulation means being: responsive to a first predetermined signal on the control terminal means to transfer a serial input bit from the serial input terminal to the serial output terminal; responsive to a second predetermined control signal on the control terminal means to transfer a parallel input bit from the parallel input terminal to the parallel output terminal; and responsive to a third predetermined signal on the control terminal means to transfer a parallel input bit from the parallel input terminal to the parallel output terminal and to transfer a serial output bit to the serial output terminal, the serial output bit comprising the modulo 2 sum of the parallel input bit applied to the parallel input terminal and a serial input bit applied to the serial input terminal, the third predetermined signal being different from the first and second predetermined signals.

Claim 28

A boundary register cell, comprising: a serial input terminal; a serial output terminal; a parallel input terminal; a parallel output terminal; control terminal means; and signal gating and accumulation means operably connected to the serial input terminal, the serial output terminal, the parallel input terminal, the parallel output terminal and the control terminal means, the signal gating and accumulation means being: responsive to a first predetermined signal on the control terminal means to transfer a serial input bit from the serial input terminal to the serial output terminal; responsive to a second predetermined control signal on the control terminal means to transfer a parallel input bit from the parallel input terminal to the parallel output terminal; and responsive to a third predetermined signal on the control terminal means to transfer a parallel input bit from the parallel input terminal to the parallel output terminal and to transfer a serial output bit to the serial output terminal, the serial output bit comprising the modulo 2 sum of the parallel input bit applied to the parallel input terminal and a serial input bit applied to the serial input terminal, the third predetermined signal being different from the first and second predetermined signals.

Claim 29

A boundary register cell as defined in claim 19, wherein the signal gating and accumulation means is responsive to a second predetermined signal on the control terminal means identical to the first predetermined signal to transfer a parallel input bit from the parallel input terminal to the parallel output terminal.

Claim 30

A boundary register cell as defined in claim 19, wherein the signal gating and accumulation means is responsive to a fourth predetermined signal on the control terminal means to transfer a serial output bit to the serial output terminal and a parallel output bit to the parallel output terminal, the serial output bit and the parallel output bit each comprising the modulo 2 sum of a serial input bit applied to the serial input terminal and a parallel input bit applied to the parallel input terminal, the fourth predetermined signal being different from the first, second and third predetermined signals.

Claim 31

A boundary register cell as defined in claim 19, wherein the signal gating and accumulation means is responsive to a fifth predetermined signal on the control terminal means to transfer a serial input bit from the serial input terminal to the serial output terminal and the parallel output terminal, the fifth predetermined signal being different from the first, second, third and fourth predetermined signals.

Claim 32

A boundary register cell as defined in claim 19, wherein: the control terminal means comprises: an input select terminal; an output select terminal; and a clock terminal; and the signal gating and accumulation means comprises: an AND gate having a first input connected to the input select terminal, a second input connected to the parallel input terminal and an output; an EXCLUSIVE OR gate having a first input connected to the output of the AND gate, a second input connected to the serial input terminal and an output; a flip flop having a data input connected to the output of the EXCLUSIVE OR gate, a clock input connected to the clock terminal and a data output connected to the serial output terminal; and a multiplexer having a first data input connected the data output of the flip flop, a second data input connected to the parallel input terminal, a select input connected to the output select terminal and a data output connected to the parallel output terminal.

Claim 33

A boundary register cell, comprising: a serial input terminal; a serial output terminal; a first parallel input/output terminal; a second parallel input/output terminal; control terminal means; and signal gating and accumulation means operably connected to the serial input terminal, the serial output terminal, the first parallel input/output terminal, the second parallel input/output terminal and the control terminal means, the signal gating and compression means being: responsive to a first predetermined signal on the control terminal means to transfer a serial input bit from the serial input terminal to the serial output terminal; responsive to a second predetermined control signal on the control terminal means to transfer a parallel input bit from the first parallel input/output terminal to the second parallel input/output terminal; responsive to a third predetermined signal on the control terminal means to transfer a parallel input bit from the first parallel input/output terminal to the second parallel input/output terminal and to apply a serial output bit to the serial output terminal, the serial output bit comprising the modulo 2 sum of the parallel input bit applied to the first parallel input/output terminal and a serial input bit applied to the serial input terminal, the third predetermined signal being different from the first and second predetermined signals; responsive to a fourth predetermined control signal on the control terminal means to transfer a parallel input bit from the second parallel input/output terminal to the first parallel input/output terminal, the fourth predetermined signal being different from the second and third predetermined signals; and responsive to a fifth predetermined signal on the control terminal means to transfer a parallel input bit from the second parallel input/output terminal to the first parallel input/output terminal and to transfer a serial output bit to the serial output terminal, the serial output bit comprising the modulo 2 sum of the parallel input bit applied to the second parallel input/output terminal and a serial input bit applied to the serial input terminal, the fifth predetermined signal being different from the first, second, third and fourth predetermined signals.

Claim 34

A boundary register cell, comprising: a serial input terminal; a serial output terminal; a first parallel input/output terminal; a second parallel input/output terminal; control terminal means; and signal gating and accumulation means operably connected to the serial input terminal, the serial output terminal, the first parallel input/output terminal, the second parallel input/output terminal and the control terminal means, the signal gating and compression means being: responsive to a first predetermined signal on the control terminal means to transfer a serial input bit from the serial input terminal to the serial output terminal; responsive to a second predetermined control signal on the control terminal means to transfer a parallel input bit from the first parallel input/output terminal to the second parallel input/output terminal; responsive to a third predetermined signal on the control terminal means to transfer a parallel input bit from the first parallel input/output terminal to the second parallel input/output terminal and to apply a serial output bit to the serial output terminal, the serial output bit comprising the modulo 2 sum of the parallel input bit applied to the first parallel input/output terminal and a serial input bit applied to the serial input terminal, the third predetermined signal being different from the first and second predetermined signals; responsive to a fourth predetermined control signal on the control terminal means to transfer a parallel input bit from the second parallel input/output terminal to the first parallel input/output terminal, the fourth predetermined signal being different from the second and third predetermined signals; and responsive to a fifth predetermined signal on the control terminal means to transfer a parallel input bit from the second parallel input/output terminal to the first parallel input/output terminal and to transfer a serial output bit to the serial output terminal, the serial output bit comprising the modulo 2 sum of the parallel input bit applied to the second parallel input/output terminal and a serial input bit applied to the serial input terminal, the fifth predetermined signal being different from the first, second, third and fourth predetermined signals.

Claim 35

A boundary register cell as defined in claim 24, wherein the signal gating and accumulation means is: responsive to a second predetermined signal on the control terminal means identical to the first predetermined signal to transfer a parallel input bit from the parallel input terminal to the parallel output terminal; and responsive to the fourth predetermined signal on the control terminal means to transfer a serial input bit from the serial input terminal to the serial output terminal.

Claim 36

A boundary register cell as defined in claim 24, wherein the signal gating and accumulation means is: responsive to a sixth predetermined signal on the control terminal means to transfer a serial output bit to the serial output terminal and a parallel output bit to the second parallel input/output terminal, the serial output bit and the parallel output bit each comprising the modulo 2 sum of a serial input bit applied to the serial input terminal and a parallel input bit applied to the first parallel input/output terminal, the sixth predetermined signal being different from the first, second, third, fourth and fifth predetermined signals; and responsive to a seventh predetermined signal on the control terminal means to transfer a serial output bit to the serial output terminal and a parallel output bit to the first parallel input/output terminal, the serial output bit and the parallel output bit each comprising the modulo 2 sum of a serial input bit applied to the serial input terminal and a parallel input bit applied to the second parallel input/output terminal, the seventh predetermined signal being different from the first, second, third, fourth, fifth and sixth predetermined signals.

Claim 37

A boundary register cell as defined in claim 24, wherein the signal gating and accumulation means is: responsive to an eighth predetermined signal on the control terminal means to transfer a serial input bit from the serial input terminal to the serial output terminal and the second parallel input/output terminal, the eighth predetermined signal being different from the first, second, third, fourth, fifth, sixth and seventh predetermined signals; and responsive to a ninth predetermined signal on the control terminal means to transfer a serial input bit from the serial input terminal to the serial output terminal and the first parallel input/output terminal, the ninth predetermined signal being different from the first, second, third, fourth, fifth, sixth, seventh and eighth predetermined signals.

Claim 38

A boundary register cell as defined in claim 24, wherein: the control terminal means comprises: a first input select terminal; a second input select terminal; a first output select terminal; a second output select terminal; a direction select terminal; and a clock terminal; and the signal gating and accumulation means comprises: a first AND gate having a first input connected to the first input select terminal, a second input connected to the first parallel input/output terminal, a third input connected the direction select terminal, and an output; an invertor having an input connected to the direction select terminal and an output; a second AND gate having a first input connected to the second input select terminal, a second input connected to the second parallel input/output terminal, a third input connected to the output of the invertor and an output; an OR gate having a first input connected to the output of the first AND gate, a second input connected to the output of the second AND gate and an output; an EXCLUSIVE OR gate having a first input connected to the output of the OR gate, a second input connected to the serial input terminal and an output; a flip flop having a data input connected to the output of the EXCLUSIVE OR gate, a clock input connected to the clock terminal and a data output connected to the serial output terminal; and a first multiplexer having a first data input connected to the data output of the flip flop, a second data input connected to the first parallel input/output terminal, a select input connected to the first output select terminal and a data output; a first tri-state buffer having an enable input connected to the direction select terminal, a data input connected to data output of the first multiplexer and a data output connected to the second parallel input/output terminal; a second multiplexer having a first data input connected to the data output of the flip flop, a second data input connected to the second parallel input/output terminal, a select input connected to the second output select terminal and a data output; a second tri-state buffer having an enable input connected to the output of the invertor, a data input connected to data output of the second multiplexer and a data output connected to the first parallel input/output terminal.

Claim 39

A boundary register, comprising: a plurality of boundary register cells as defined in claim 19 or claim 24, said boundary register cells connected in series, serial output terminal to serial input terminal to comprise a chain of cells; and a control bus connected to the control terminal means of each cell.

Claim 40

A boundary register as defined in claim 29, further comprising means for connecting ends of the chain of boundary register cells to define a ring register.